17457634. CHANNEL PROTECTION OF GATE-ALL-AROUND DEVICES FOR PERFORMANCE OPTIMIZATION simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
CHANNEL PROTECTION OF GATE-ALL-AROUND DEVICES FOR PERFORMANCE OPTIMIZATION
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Maruf Amin Bhuiyan of Albany NY (US)
Julien Frougier of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
Eric Miller of Watervliet NY (US)
CHANNEL PROTECTION OF GATE-ALL-AROUND DEVICES FOR PERFORMANCE OPTIMIZATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17457634 titled 'CHANNEL PROTECTION OF GATE-ALL-AROUND DEVICES FOR PERFORMANCE OPTIMIZATION
Simplified Explanation
The abstract describes a gate-all-around device that consists of multiple channel layers stacked vertically over a substrate. Inner spacers are placed between each channel layer, and source/drain regions are in contact with the ends of some of the channel layers. A dielectric layer is present on the ends of other channel layers in a spacer region adjacent to the source/drain regions. The width of the dielectric layer and the corresponding channel layers is equal to the width of the inner spacer.
- The gate-all-around device includes multiple vertically stacked channel layers.
- Inner spacers are placed between each channel layer.
- Source/drain regions are in contact with some of the channel layers.
- A dielectric layer is present on the ends of other channel layers in a spacer region.
- The width of the dielectric layer and corresponding channel layers matches the width of the inner spacer.
Potential Applications
- Semiconductor industry
- Electronics manufacturing
- Integrated circuits
- Transistors
Problems Solved
- Improved performance and efficiency of gate-all-around devices
- Enhanced control over the flow of electrical current
- Reduction in power consumption
- Increased integration density
Benefits
- Higher performance and efficiency in gate-all-around devices
- Improved control over electrical current flow
- Lower power consumption
- Increased integration density for more compact devices
Original Abstract Submitted
A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.
