17457448. NANOSHEET EPITAXY WITH FULL BOTTOM ISOLATION simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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NANOSHEET EPITAXY WITH FULL BOTTOM ISOLATION

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Julien Frougier of Albany NY (US)

Andrew M. Greene of Slingerlands NY (US)

Ruilong Xie of Niskayuna NY (US)

Lan Yu of Voorheesville NY (US)

PIETRO Montanini of Albany NY (US)

NANOSHEET EPITAXY WITH FULL BOTTOM ISOLATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17457448 titled 'NANOSHEET EPITAXY WITH FULL BOTTOM ISOLATION

Simplified Explanation

The patent application describes a technology involving vertically aligned semiconductor channel layers stacked on top of each other, separated by a gate stack material. It also includes a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, with a horizontal lower surface of the p-FET source drain epitaxy region adjacent to a horizontal upper surface of an undoped silicon epitaxy.

  • The technology involves the formation of multiple stacks of nanosheet layers on a substrate, with each stack consisting of alternating layers of sacrificial and semiconductor channel layers.
  • Sacrificial gates are formed across each stack to facilitate the fabrication process.
  • An undoped silicon epitaxy is formed between the stacks to provide additional functionality.

Potential Applications

  • This technology can be applied in the field of semiconductor manufacturing and integrated circuit design.
  • It can be used to create advanced transistors and other electronic devices with improved performance and functionality.

Problems Solved

  • The technology addresses the need for vertically aligned semiconductor channel layers and gate stack materials in the fabrication of advanced electronic devices.
  • It solves the problem of integrating heavily doped p-type field effect transistor (p-FET) source drain epitaxy regions with the semiconductor channel layers.

Benefits

  • The technology enables the creation of vertically stacked semiconductor channel layers, allowing for increased device density and improved performance.
  • It provides a solution for integrating heavily doped p-FET source drain epitaxy regions, which can enhance the functionality of electronic devices.
  • The use of sacrificial gates simplifies the fabrication process and allows for precise control over the device structure.


Original Abstract Submitted

Semiconductor channel layers vertically aligned and stacked one on top of another, separated by a gate stack material wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy. Forming a first stack, second stack and third stack of nanosheet layers on a substrate, each including alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another, forming a first sacrificial gate across the first stack, a second sacrificial gate across the second stack and a third sacrificial gate across the third stack, forming an undoped silicon epitaxy between the first and the second stacks and between the second and the third stacks.

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