17456068. INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS simplified abstract (QUALCOMM Incorporated)

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INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS

Organization Name

QUALCOMM Incorporated

Inventor(s)

Hong Bok We of San Diego CA (US)

Joan Rey Villarba Buot of Escondido CA (US)

Michelle Yejin Kim of San Diego CA (US)

Kuiwon Kang of San Diego CA (US)

Aniket Patil of San Diego CA (US)

INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17456068 titled 'INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS

Simplified Explanation

The abstract describes a patent application for integrated circuit (IC) packages that use a package substrate with a double side embedded trace substrate (ETS). This allows for a thinner substrate in the IC package, reducing the overall height of the package while supporting higher density input/output (I/O) connections. The double side ETS includes two adjacent ETS metallization layers with metal traces embedded in an insulating layer. These metal traces can be electrically coupled to each other through vertical interconnect accesses (vias) to provide signal routing paths between the embedded metal traces.

  • IC packages use a package substrate with a double side embedded trace substrate (ETS).
  • The double side ETS includes two adjacent ETS metallization layers with embedded metal traces.
  • The embedded metal traces can be electrically coupled to each other through vertical interconnect accesses (vias).
  • This allows for a thinner substrate in the IC package, reducing overall height.
  • The technology supports higher density input/output (I/O) connections.

Potential Applications

  • Integrated circuit packaging
  • Electronics manufacturing

Problems Solved

  • Reduces the overall height of IC packages
  • Supports higher density I/O connections

Benefits

  • Thinner substrate in IC packages
  • Increased density of I/O connections
  • Improved signal routing paths


Original Abstract Submitted

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.

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