17455937. REDUCED PARASITIC RESISTANCE TWO-DIMENSIONAL MATERIAL FIELD-EFFECT TRANSISTOR simplified abstract (International Business Machines Corporation)
REDUCED PARASITIC RESISTANCE TWO-DIMENSIONAL MATERIAL FIELD-EFFECT TRANSISTOR
Organization Name
International Business Machines Corporation
Inventor(s)
Kangguo Cheng of Schenectady NY (US)
Andrew Gaul of Halfmoon NY (US)
Julien Frougier of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
REDUCED PARASITIC RESISTANCE TWO-DIMENSIONAL MATERIAL FIELD-EFFECT TRANSISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 17455937 titled 'REDUCED PARASITIC RESISTANCE TWO-DIMENSIONAL MATERIAL FIELD-EFFECT TRANSISTOR
Simplified Explanation
The abstract describes a new approach to creating a field-effect transistor device using a two-dimensional material. The device includes a channel made of the two-dimensional material on a substrate, with a high-k gate dielectric layer covering the channel and extending under and around a sidewall spacer. The device also has a metal gate located inside the high-k gate dielectric and over the channel. The source/drain is positioned on a portion of the two-dimensional material on the substrate, adjacent to the sidewall spacer, and is made of a bi-layer metal.
- The field-effect transistor device is formed using a two-dimensional material.
- The device includes a channel made of the two-dimensional material on a substrate.
- A high-k gate dielectric layer is applied on the channel and extends under and around a sidewall spacer.
- A metal gate is located inside the high-k gate dielectric and over the channel.
- The source/drain is positioned on a portion of the two-dimensional material on the substrate.
- The source/drain is composed of a bi-layer metal.
Potential Applications
- This technology can be used in the manufacturing of field-effect transistor devices.
- It may find applications in various electronic devices, such as computers, smartphones, and other integrated circuits.
Problems Solved
- The approach solves the problem of creating a field-effect transistor device using a two-dimensional material.
- It addresses the challenge of forming a high-k gate dielectric layer that extends under and around a sidewall spacer.
Benefits
- The use of a two-dimensional material in the device can offer improved performance and efficiency.
- The high-k gate dielectric layer provides enhanced gate control and reduced leakage current.
- The bi-layer metal composition of the source/drain can improve conductivity and overall device performance.
Original Abstract Submitted
An approach to forming a field-effect transistor device formed with a two-dimensional material. The field-effect transistor device includes a channel composed of the two-dimensional material on a substrate and a high-k gate dielectric on the channel and extending under a sidewall spacer and around the sidewall spacer. The field-effect transistor includes a metal gate that is inside the high-k gate dielectric and over the channel. The source/drain is on a portion the two-dimensional material on the substrate. The source/drain abuts the sidewall spacer and is composed of a bi-layer metal.
