17453882. GATE-ALL-AROUND NANOSHEET-FET WITH VARIABLE CHANNEL GEOMETRIES FOR PERFORMANCE OPTIMIZATION simplified abstract (International Business Machines Corporation)

GATE-ALL-AROUND NANOSHEET-FET WITH VARIABLE CHANNEL GEOMETRIES FOR PERFORMANCE OPTIMIZATION

Organization Name

International Business Machines Corporation

Inventor(s)

Julien Frougier of Albany NY (US)

Ruilong Xie of Niskayuna NY (US)

Heng Wu of Guilderland NY (US)

Chen Zhang of Guilderland NY (US)

Alexander Reznicek of Troy NY (US)

GATE-ALL-AROUND NANOSHEET-FET WITH VARIABLE CHANNEL GEOMETRIES FOR PERFORMANCE OPTIMIZATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17453882 titled 'GATE-ALL-AROUND NANOSHEET-FET WITH VARIABLE CHANNEL GEOMETRIES FOR PERFORMANCE OPTIMIZATION

Simplified Explanation

The abstract describes a semiconductor device that consists of two nanosheets stacked on top of each other on a substrate. The first nanosheet is tapered in both the Y-direction (vertical) and the X-direction (horizontal), with a specific width and length. The second nanosheet is also tapered in the Y-direction and X-direction, but with different dimensions. The substrate itself has a tapered surface in the Y-direction.

• The semiconductor device consists of two nanosheets stacked on top of each other.
• The first nanosheet is tapered in both the vertical and horizontal directions.
• The second nanosheet is also tapered in both directions, but with different dimensions.
• The substrate has a tapered surface in the vertical direction.

Potential applications of this technology:

• This semiconductor device could be used in electronic devices such as transistors or integrated circuits.
• The unique tapering of the nanosheets and substrate could enhance the performance and efficiency of these electronic devices.

Problems solved by this technology:

• The tapered nanosheets and substrate provide a more precise control over the electrical properties of the semiconductor device.
• This could help overcome challenges related to miniaturization and performance limitations in electronic devices.

Benefits of this technology:

• The tapered design allows for better control over the flow of electrons in the semiconductor device.
• This can lead to improved performance, efficiency, and reliability of electronic devices.
• The unique structure of the nanosheets and substrate could enable the development of smaller and more powerful electronic devices.

Original Abstract Submitted

A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width Wand the first nanosheet is tapered in the X-direction to have a length L. Wherein the widths Wand Ware different from each other and the lengths Land Lare different from each other and wherein the substrate includes a tapered surface in the Y-direction.