17453670. ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA simplified abstract (International Business Machines Corporation)

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ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA

Organization Name

International Business Machines Corporation

Inventor(s)

Koichi Motoyama of Clifton Park NY (US)

CHANRO Park of CLIFTON PARK NY (US)

Hsueh-Chung Chen of Cohoes NY (US)

Chih-Chao Yang of Glenmont NY (US)

ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA - A simplified explanation of the abstract

This abstract first appeared for US patent application 17453670 titled 'ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA

Simplified Explanation

The patent application describes a semiconductor device and a method of fabricating it. The device includes multiple bottom lines, with top vias and electronic fuses (eFuses) arranged on top of them. Each eFuse is a smaller via compared to the top vias. Additionally, there are top lines arranged on top of the top vias and eFuses.

  • The semiconductor device includes multiple bottom lines.
  • Top vias and electronic fuses (eFuses) are arranged on top of the bottom lines.
  • Each eFuse is a smaller via compared to the top vias.
  • Top lines are arranged on top of the top vias and eFuses.

Potential applications of this technology:

  • Integrated circuits
  • Microprocessors
  • Memory devices
  • Power management systems

Problems solved by this technology:

  • Efficient arrangement of top vias and eFuses on top of bottom lines
  • Smaller critical dimension of eFuses allows for more compact designs
  • Improved functionality and reliability of semiconductor devices

Benefits of this technology:

  • Enhanced performance and functionality of semiconductor devices
  • Increased integration and miniaturization capabilities
  • Improved manufacturing efficiency and cost-effectiveness


Original Abstract Submitted

Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.

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