17412665. METHOD AND STRUCTURE FOR IMPROVED MEMORY INTEGRITY AT ARRAY BOUNDARIES simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

METHOD AND STRUCTURE FOR IMPROVED MEMORY INTEGRITY AT ARRAY BOUNDARIES

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Jun-Yao Chen of Taoyuan City (TW)

Hung Cho Wang of Taipei (TW)

Harry-Hak-Lay Chuang of Zhubei City (TW)

METHOD AND STRUCTURE FOR IMPROVED MEMORY INTEGRITY AT ARRAY BOUNDARIES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17412665 titled 'METHOD AND STRUCTURE FOR IMPROVED MEMORY INTEGRITY AT ARRAY BOUNDARIES

Simplified Explanation

The patent application describes a semiconductor structure with a memory array that is positioned above a substrate. The memory array consists of multiple rows and columns. Within the memory array, there are two adjacent memory cells at the same height above the substrate. The second memory cell is located at the edge of the memory array, separating the first memory cell from the edge. Additionally, the top surface of the first memory cell is recessed compared to the top surface of the second memory cell.

• The semiconductor structure includes a memory array with multiple rows and columns.
• Two adjacent memory cells are positioned at the same elevation above the substrate.
• The second memory cell is located at the edge of the memory array, separating the first memory cell from the edge.
• The top surface of the first memory cell is recessed relative to the top surface of the second memory cell.

Potential Applications:

• This semiconductor structure can be used in various memory devices, such as flash memory or random-access memory (RAM) chips.
• It can be implemented in electronic devices like smartphones, tablets, computers, and other devices that require memory storage.

Problems Solved:

• The arrangement of the memory cells in this structure allows for efficient use of space within the memory array.
• The recessed top surface of the first memory cell helps in reducing the overall size of the semiconductor structure.

Benefits:

• The compact design of the memory array allows for higher memory density, enabling more storage capacity in a smaller area.
• The efficient use of space helps in reducing the manufacturing cost of memory devices.
• The recessed top surface of the first memory cell contributes to improved performance and reliability of the semiconductor structure.

Original Abstract Submitted

The present disclosure relate to semiconductor structure that includes a substrate and a memory array. The memory array is spaced over the substrate and has a plurality of rows and a plurality of columns. Further, the memory array comprises a first memory cell and a second memory cell that are adjacent at a common elevation above the substrate. The second memory cell is at an edge of the memory array and separates the first memory cell from the edge, and a top surface of the first memory cell is recessed relative to a top surface of the second memory cell.