17412641. SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chin-Hua Wang of New Taipei City (TW)
Shu-Shen Yeh of Taoyuan City (TW)
Po-Chen Lai of Hsinchu County (TW)
Po-Yao Lin of Zhudong Township (TW)
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK - A simplified explanation of the abstract
This abstract first appeared for US patent application 17412641 titled 'SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
Simplified Explanation
The patent application describes a semiconductor structure that includes a first substrate with conductive pads and bumps, as well as a multi-tiered solder-resist structure. The solder-resist structure separates the conductive bumps from each other.
- The semiconductor structure includes a first substrate with conductive pads and bumps.
- A multi-tiered solder-resist structure is placed on the substrate.
- The solder-resist structure has different widths at different heights over the substrate.
- The solder-resist structure contacts the sidewalls of the conductive bumps.
- The solder-resist structure separates the conductive bumps from each other.
Potential Applications
- Semiconductor manufacturing
- Electronics industry
- Integrated circuit production
Problems Solved
- Preventing short circuits between conductive bumps
- Improving the reliability of semiconductor structures
- Enhancing the performance of electronic devices
Benefits
- Increased efficiency in semiconductor manufacturing
- Reduced risk of electrical failures
- Improved functionality and durability of electronic devices
Original Abstract Submitted
Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.
