17412625. Semiconductor Package And Method simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

From WikiPatents
Jump to navigation Jump to search

Semiconductor Package And Method

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Jiun Yi Wu of Zhongli City (TW)

Chen-Hua Yu of Hsinchu (TW)

Semiconductor Package And Method - A simplified explanation of the abstract

This abstract first appeared for US patent application 17412625 titled 'Semiconductor Package And Method

Simplified Explanation

The abstract describes a structure that includes a core substrate and a redistribution structure with multiple redistribution layers. The structure also includes a first local interconnect component embedded in one of the redistribution layers, with bond pads physically contacting a metallization layer of another redistribution layer.

  • The structure includes a core substrate and a redistribution structure with multiple redistribution layers.
  • Each redistribution layer consists of a dielectric layer and a metallization layer.
  • The structure also includes a first local interconnect component embedded in one of the redistribution layers.
  • The first local interconnect component has a substrate, an interconnect structure, and bond pads.
  • The bond pads of the first local interconnect component physically contact a metallization layer of another redistribution layer.
  • The metallization layer of the second redistribution layer contains first conductive vias.
  • The dielectric layer of the first redistribution layer encapsulates the first local interconnect component.

Potential Applications

  • Integrated circuit packaging
  • Semiconductor devices
  • Electronic components

Problems Solved

  • Simplifies the structure of integrated circuits
  • Enables efficient redistribution of signals within the circuit
  • Provides a compact and reliable interconnect solution

Benefits

  • Improved performance and functionality of integrated circuits
  • Enhanced signal transmission and connectivity
  • Reduced size and complexity of circuit packaging


Original Abstract Submitted

In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.