17383849. METHOD FOR CALIBRATING ALIGNMENT OF WAFER AND LITHOGRAPHY SYSTEM simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

METHOD FOR CALIBRATING ALIGNMENT OF WAFER AND LITHOGRAPHY SYSTEM

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chang-Jen Chen of Hsinchu County (TW)

Wen-Yun Wang of Taipei City (TW)

Yen-Chun Chen of Hsinchu (TW)

Po-Ting Yeh of Hsinchu City (TW)

METHOD FOR CALIBRATING ALIGNMENT OF WAFER AND LITHOGRAPHY SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 17383849 titled 'METHOD FOR CALIBRATING ALIGNMENT OF WAFER AND LITHOGRAPHY SYSTEM

Simplified Explanation

The patent application describes a method for calibrating the alignment of a wafer used in semiconductor manufacturing. Here are the key points:

• The method involves obtaining simulation results of alignment position deviation (APD) from multiple mark profiles on the wafer.
• An alignment analysis is performed on a specific region of the wafer using a light beam.
• The measured APD of the mark region is obtained based on the response of the light beam.
• The measured APD is then compared with the APD simulation results to obtain alignment calibration data.
• This alignment calibration data is used to perform an exposure process on the wafer using a mask.

Potential applications of this technology:

• Semiconductor manufacturing: This method can be used in the production of integrated circuits and other semiconductor devices to ensure accurate alignment of the wafer during the manufacturing process.

Problems solved by this technology:

• Alignment accuracy: By calibrating the alignment of the wafer using simulation results and measured APD, this method helps to improve the accuracy of alignment during the manufacturing process.

Benefits of this technology:

• Improved manufacturing yield: Accurate alignment of the wafer can lead to better quality control and higher yield in semiconductor manufacturing.
• Cost savings: By optimizing the alignment process, this method can help reduce material waste and improve overall efficiency in semiconductor manufacturing.

Original Abstract Submitted

A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.