17377634. METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chih-Teng Liao of Hsinchu (TW)
METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17377634 titled 'METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL
Simplified Explanation
The abstract describes a method of manufacturing integrated circuits that involves a polysilicon etch process. During this process, a wafer with an etch poly pattern is placed in a reactor chamber and exposed to an activated etchant. The temperature conditions within the reactor chamber are adjusted to increase polymeric deposition on the wafer's upper surface.
- The method involves a polysilicon etch process in the manufacturing of integrated circuits.
- A wafer with an etch poly pattern is loaded into a reactor chamber.
- The wafer is exposed to an activated etchant during the etch process.
- Temperature conditions within the reactor chamber are adjusted to enhance polymeric deposition on the wafer's upper surface.
Potential Applications
- Manufacturing of integrated circuits
- Semiconductor industry
Problems Solved
- Enhances polymeric deposition during the polysilicon etch process
- Improves the manufacturing process of integrated circuits
Benefits
- Increased polymeric deposition on the wafer's upper surface
- Improved efficiency and effectiveness of the polysilicon etch process
- Enhanced quality and performance of integrated circuits
Original Abstract Submitted
Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.
