18510991. CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Yu-Ling Hsu of Tainan City (TW)
Ping-Cheng Li of Kaohsiung City (TW)
Hung-Ling Shih of Tainan City (TW)
Po-Wei Liu of Tainan City (TW)
Wen-Tuo Huang of Tainan City (TW)
Yong-Shiuan Tsair of Tainan City (TW)
Chia-Sheng Lin of Tainan City (TW)
Shih Kuang Yang of Tainan City (TW)
CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW - A simplified explanation of the abstract
This abstract first appeared for US patent application 18510991 titled 'CONTROL GATE STRAP LAYOUT TO IMPROVE A WORD LINE ETCH PROCESS WINDOW
Simplified Explanation
The patent application is focused on a control gate layout that enhances the etch process window for word lines in an integrated chip memory array.
- Integrated chip comprises memory array, erase gate, word line, and control gate
- Control gate is elongated along a row, positioned between and borders erase gate and word line
- Control gate has a pad region protruding towards erase gate and word line
- Width of pad region is spread between word-line and erase-gate sides of control gate
Potential Applications
- Semiconductor manufacturing
- Memory chip production
- Integrated circuit design
Problems Solved
- Improving etch process window for word lines
- Enhancing control gate layout efficiency
- Optimizing memory array performance
Benefits
- Increased reliability of memory arrays
- Enhanced chip performance
- Improved manufacturing process efficiency
Original Abstract Submitted
Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Ling Hsu of Tainan City (TW)
- Ping-Cheng Li of Kaohsiung City (TW)
- Hung-Ling Shih of Tainan City (TW)
- Po-Wei Liu of Tainan City (TW)
- Wen-Tuo Huang of Tainan City (TW)
- Yong-Shiuan Tsair of Tainan City (TW)
- Chia-Sheng Lin of Tainan City (TW)
- Shih Kuang Yang of Tainan City (TW)
- H01L29/423
- H01L21/265
- H01L21/28
- H01L21/3213
- H01L23/522
- H01L23/528
- H01L29/40
- H01L29/66
- H01L29/788