Difference between revisions of "Micron Technology, Inc. patent applications published on November 30th, 2023"
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==Patent applications for Micron Technology, Inc. on November 30th, 2023== | ==Patent applications for Micron Technology, Inc. on November 30th, 2023== | ||
− | ===VOLTAGE TRACKING CIRCUIT ([[US Patent Application 17824479. VOLTAGE TRACKING CIRCUIT simplified abstract|17824479]])=== | + | ===VOLTAGE TRACKING CIRCUIT ([[US Patent Application 17824479. VOLTAGE TRACKING CIRCUIT simplified abstract (Micron Technology, Inc.)|17824479]])=== |
Line 39: | Line 9: | ||
− | ===LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT ([[US Patent Application 17824749. LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT simplified abstract|17824749]])=== | + | ===LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT ([[US Patent Application 17824749. LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT simplified abstract (Micron Technology, Inc.)|17824749]])=== |
Line 47: | Line 17: | ||
− | ===CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17804153. CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE simplified abstract|17804153]])=== | + | ===CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17804153. CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE simplified abstract (Micron Technology, Inc.)|17804153]])=== |
Line 55: | Line 25: | ||
− | ===TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS ([[US Patent Application 17752354. TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS simplified abstract|17752354]])=== | + | ===TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS ([[US Patent Application 17752354. TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS simplified abstract (Micron Technology, Inc.)|17752354]])=== |
Line 63: | Line 33: | ||
− | ===SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION ([[US Patent Application 17824725. SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION simplified abstract|17824725]])=== | + | ===SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION ([[US Patent Application 17824725. SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION simplified abstract (Micron Technology, Inc.)|17824725]])=== |
Line 71: | Line 41: | ||
− | ===CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES ([[US Patent Application 17806888. CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES simplified abstract|17806888]])=== | + | ===CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES ([[US Patent Application 17806888. CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES simplified abstract (Micron Technology, Inc.)|17806888]])=== |
Line 79: | Line 49: | ||
− | ===Data Recorders of Autonomous Vehicles ([[US Patent Application 18326972. Data Recorders of Autonomous Vehicles simplified abstract|18326972]])=== | + | ===Data Recorders of Autonomous Vehicles ([[US Patent Application 18326972. Data Recorders of Autonomous Vehicles simplified abstract (Micron Technology, Inc.)|18326972]])=== |
Line 87: | Line 57: | ||
− | ===BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE ([[US Patent Application 18326984. BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE simplified abstract|18326984]])=== | + | ===BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE ([[US Patent Application 18326984. BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE simplified abstract (Micron Technology, Inc.)|18326984]])=== |
Line 95: | Line 65: | ||
− | ===DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING ([[US Patent Application 18202584. DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING simplified abstract|18202584]])=== | + | ===DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING ([[US Patent Application 18202584. DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING simplified abstract (Micron Technology, Inc.)|18202584]])=== |
Line 103: | Line 73: | ||
− | ===APPARATUSES AND METHODS FOR COMMAND DECODING ([[US Patent Application 17752573. APPARATUSES AND METHODS FOR COMMAND DECODING simplified abstract|17752573]])=== | + | ===APPARATUSES AND METHODS FOR COMMAND DECODING ([[US Patent Application 17752573. APPARATUSES AND METHODS FOR COMMAND DECODING simplified abstract (Micron Technology, Inc.)|17752573]])=== |
Line 111: | Line 81: | ||
− | ===APPARATUSES AND METHODS FOR COMMAND DECODING ([[US Patent Application 17752605. APPARATUSES AND METHODS FOR COMMAND DECODING simplified abstract|17752605]])=== | + | ===APPARATUSES AND METHODS FOR COMMAND DECODING ([[US Patent Application 17752605. APPARATUSES AND METHODS FOR COMMAND DECODING simplified abstract (Micron Technology, Inc.)|17752605]])=== |
Line 119: | Line 89: | ||
− | ===MEMORY DEVICES FOR MULTIPLE READ OPERATIONS ([[US Patent Application 18232949. MEMORY DEVICES FOR MULTIPLE READ OPERATIONS simplified abstract|18232949]])=== | + | ===MEMORY DEVICES FOR MULTIPLE READ OPERATIONS ([[US Patent Application 18232949. MEMORY DEVICES FOR MULTIPLE READ OPERATIONS simplified abstract (Micron Technology, Inc.)|18232949]])=== |
Line 127: | Line 97: | ||
− | ===PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES ([[US Patent Application 17829046. PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES simplified abstract|17829046]])=== | + | ===PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES ([[US Patent Application 17829046. PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES simplified abstract (Micron Technology, Inc.)|17829046]])=== |
Line 135: | Line 105: | ||
− | ===APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE ([[US Patent Application 18202659. APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE simplified abstract|18202659]])=== | + | ===APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE ([[US Patent Application 18202659. APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE simplified abstract (Micron Technology, Inc.)|18202659]])=== |
Line 143: | Line 113: | ||
− | ===APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION ([[US Patent Application 17825600. APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION simplified abstract|17825600]])=== | + | ===APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION ([[US Patent Application 17825600. APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION simplified abstract (Micron Technology, Inc.)|17825600]])=== |
Line 151: | Line 121: | ||
− | ===APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT ([[US Patent Application 17827582. APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT simplified abstract|17827582]])=== | + | ===APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT ([[US Patent Application 17827582. APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT simplified abstract (Micron Technology, Inc.)|17827582]])=== |
Line 159: | Line 129: | ||
− | ===METHODS OF CONFIGURING A MEMORY ([[US Patent Application 18232386. METHODS OF CONFIGURING A MEMORY simplified abstract|18232386]])=== | + | ===METHODS OF CONFIGURING A MEMORY ([[US Patent Application 18232386. METHODS OF CONFIGURING A MEMORY simplified abstract (Micron Technology, Inc.)|18232386]])=== |
Line 167: | Line 137: | ||
− | ===WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE ([[US Patent Application 17752785. WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE simplified abstract|17752785]])=== | + | ===WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE ([[US Patent Application 17752785. WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)|17752785]])=== |
Line 175: | Line 145: | ||
− | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17752207. Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract|17752207]])=== | + | ===Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17752207. Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract (Micron Technology, Inc.)|17752207]])=== |
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− | ===PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17825439. PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE simplified abstract|17825439]])=== | + | ===PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE ([[US Patent Application 17825439. PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE simplified abstract (Micron Technology, Inc.)|17825439]])=== |
Line 191: | Line 161: | ||
− | ===ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM ([[US Patent Application 17752590. ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM simplified abstract|17752590]])=== | + | ===ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM ([[US Patent Application 17752590. ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM simplified abstract (Micron Technology, Inc.)|17752590]])=== |
Line 199: | Line 169: | ||
− | ===MEDIA MANAGEMENT ([[US Patent Application 17824384. MEDIA MANAGEMENT simplified abstract|17824384]])=== | + | ===MEDIA MANAGEMENT ([[US Patent Application 17824384. MEDIA MANAGEMENT simplified abstract (Micron Technology, Inc.)|17824384]])=== |
Line 207: | Line 177: | ||
− | ===INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES ([[US Patent Application 18109830. INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES simplified abstract|18109830]])=== | + | ===INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES ([[US Patent Application 18109830. INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES simplified abstract (Micron Technology, Inc.)|18109830]])=== |
Line 215: | Line 185: | ||
− | ===NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS ([[US Patent Application 17827006. NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS simplified abstract|17827006]])=== | + | ===NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS ([[US Patent Application 17827006. NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)|17827006]])=== |
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− | ===MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER ([[US Patent Application 17826776. MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER simplified abstract|17826776]])=== | + | ===MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER ([[US Patent Application 17826776. MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER simplified abstract (Micron Technology, Inc.)|17826776]])=== |
Line 231: | Line 201: | ||
− | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804247. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract|17804247]])=== | + | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804247. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract (Micron Technology, Inc.)|17804247]])=== |
Line 239: | Line 209: | ||
− | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804251. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract|17804251]])=== | + | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804251. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract (Micron Technology, Inc.)|17804251]])=== |
Line 247: | Line 217: | ||
− | ===RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING ([[US Patent Application 17825695. RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING simplified abstract|17825695]])=== | + | ===RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING ([[US Patent Application 17825695. RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING simplified abstract (Micron Technology, Inc.)|17825695]])=== |
Line 255: | Line 225: | ||
− | ===MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS ([[US Patent Application 17804530. MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS simplified abstract|17804530]])=== | + | ===MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS ([[US Patent Application 17804530. MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)|17804530]])=== |
Line 263: | Line 233: | ||
− | ===TRANSISTOR WITH GATE ATTACHED FIELD PLATE ([[US Patent Application 17752610. TRANSISTOR WITH GATE ATTACHED FIELD PLATE simplified abstract|17752610]])=== | + | ===TRANSISTOR WITH GATE ATTACHED FIELD PLATE ([[US Patent Application 17752610. TRANSISTOR WITH GATE ATTACHED FIELD PLATE simplified abstract (Micron Technology, Inc.)|17752610]])=== |
Line 271: | Line 241: | ||
− | ===TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE ([[US Patent Application 18359795. TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE simplified abstract|18359795]])=== | + | ===TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE ([[US Patent Application 18359795. TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE simplified abstract (Micron Technology, Inc.)|18359795]])=== |
Line 279: | Line 249: | ||
− | ===CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE ([[US Patent Application 18448815. CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE simplified abstract|18448815]])=== | + | ===CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE ([[US Patent Application 18448815. CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE simplified abstract (Micron Technology, Inc.)|18448815]])=== |
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− | ===INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS ([[US Patent Application 17804789. INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS simplified abstract|17804789]])=== | + | ===INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS ([[US Patent Application 17804789. INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS simplified abstract (Micron Technology, Inc.)|17804789]])=== |
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− | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804234. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract|17804234]])=== | + | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804234. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract (Micron Technology, Inc.)|17804234]])=== |
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− | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804270. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract|17804270]])=== | + | ===MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 17804270. MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract (Micron Technology, Inc.)|17804270]])=== |
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− | ===ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING ([[US Patent Application 17804752. ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING simplified abstract|17804752]])=== | + | ===ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING ([[US Patent Application 17804752. ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING simplified abstract (Micron Technology, Inc.)|17804752]])=== |
Line 319: | Line 289: | ||
− | ===Memory Circuitry And Method Used In Forming Memory Circuitry ([[US Patent Application 17751978. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract|17751978]])=== | + | ===Memory Circuitry And Method Used In Forming Memory Circuitry ([[US Patent Application 17751978. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)|17751978]])=== |
Line 327: | Line 297: | ||
− | ===Memory Circuitry And Method Used In Forming Memory Circuitry ([[US Patent Application 17869586. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract|17869586]])=== | + | ===Memory Circuitry And Method Used In Forming Memory Circuitry ([[US Patent Application 17869586. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)|17869586]])=== |
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− | ===Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17879140. Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract|17879140]])=== | + | ===Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17879140. Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract (Micron Technology, Inc.)|17879140]])=== |
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− | ===METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 18359792. METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract|18359792]])=== | + | ===METHODS OF FORMING MICROELECTRONIC DEVICES ([[US Patent Application 18359792. METHODS OF FORMING MICROELECTRONIC DEVICES simplified abstract (Micron Technology, Inc.)|18359792]])=== |
Revision as of 07:03, 5 December 2023
Contents
- 1 Patent applications for Micron Technology, Inc. on November 30th, 2023
- 1.1 VOLTAGE TRACKING CIRCUIT (17824479)
- 1.2 LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT (17824749)
- 1.3 CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE (17804153)
- 1.4 TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS (17752354)
- 1.5 SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION (17824725)
- 1.6 CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES (17806888)
- 1.7 Data Recorders of Autonomous Vehicles (18326972)
- 1.8 BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE (18326984)
- 1.9 DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING (18202584)
- 1.10 APPARATUSES AND METHODS FOR COMMAND DECODING (17752573)
- 1.11 APPARATUSES AND METHODS FOR COMMAND DECODING (17752605)
- 1.12 MEMORY DEVICES FOR MULTIPLE READ OPERATIONS (18232949)
- 1.13 PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES (17829046)
- 1.14 APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE (18202659)
- 1.15 APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION (17825600)
- 1.16 APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT (17827582)
- 1.17 METHODS OF CONFIGURING A MEMORY (18232386)
- 1.18 WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE (17752785)
- 1.19 Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17752207)
- 1.20 PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE (17825439)
- 1.21 ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM (17752590)
- 1.22 MEDIA MANAGEMENT (17824384)
- 1.23 INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES (18109830)
- 1.24 NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS (17827006)
- 1.25 MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER (17826776)
- 1.26 MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804247)
- 1.27 MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804251)
- 1.28 RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING (17825695)
- 1.29 MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS (17804530)
- 1.30 TRANSISTOR WITH GATE ATTACHED FIELD PLATE (17752610)
- 1.31 TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE (18359795)
- 1.32 CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE (18448815)
- 1.33 INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS (17804789)
- 1.34 MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804234)
- 1.35 MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804270)
- 1.36 ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING (17804752)
- 1.37 Memory Circuitry And Method Used In Forming Memory Circuitry (17751978)
- 1.38 Memory Circuitry And Method Used In Forming Memory Circuitry (17869586)
- 1.39 Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17879140. Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract (Micron Technology, Inc.)|17879140]])
- 1.40 METHODS OF FORMING MICROELECTRONIC DEVICES (18359792)
Patent applications for Micron Technology, Inc. on November 30th, 2023
VOLTAGE TRACKING CIRCUIT (17824479)
Main Inventor
Leon Zlotnik
LIFESPAN FORECASTING OF MEMORY DEVICES AND PREDICTIVE DEVICE HEALTH MANAGEMENT (17824749)
Main Inventor
Manjunath Chandrashekaraiah
CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE (17804153)
Main Inventor
Jeremy BINFET
TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS (17752354)
Main Inventor
Roberto Izzi
SELECTIVE SINGLE-LEVEL MEMORY CELL OPERATION (17824725)
Main Inventor
Donghua Zhou
CAPTURING VIDEO DATA OF EVENTS ASSOCIATED WITH VEHICLES (17806888)
Main Inventor
Alyssa SCARBROUGH
Data Recorders of Autonomous Vehicles (18326972)
Main Inventor
Gil Golov
BLACK BOX DATA RECORDER FOR AUTONOMOUS DRIVING VEHICLE (18326984)
Main Inventor
Gil Golov
DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING (18202584)
Main Inventor
Peter Mayer
APPARATUSES AND METHODS FOR COMMAND DECODING (17752573)
Main Inventor
YUTAKA UEMURA
APPARATUSES AND METHODS FOR COMMAND DECODING (17752605)
Main Inventor
YUTAKA UEMURA
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS (18232949)
Main Inventor
Eric N. Lee
PMOS THRESHOLD COMPENSATION SENSE AMPLIFIER FOR FeRAM DEVICES (17829046)
Main Inventor
Tong Liu
APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE (18202659)
Main Inventor
Perry V. Lea
APPARATUSES AND METHODS FOR BIAS TEMPERATURE INSTABILITY MITIGATION (17825600)
Main Inventor
YOSHIYA KOMATSU
APPARATUSES AND METHODS FOR ARRANGING READ DATA FOR OUTPUT (17827582)
Main Inventor
Ryo Fujimaki
METHODS OF CONFIGURING A MEMORY (18232386)
Main Inventor
Pin-Chou Chiang
WORDLINE BOOST BY CHARGE SHARING IN A MEMORY DEVICE (17752785)
Main Inventor
Mattia Robustelli
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17752207)
Main Inventor
Haoyu Li
PARTIAL BLOCK HANDLING PROTOCOL IN A NON-VOLATILE MEMORY DEVICE (17825439)
Main Inventor
Zhongguang Xu
ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM (17752590)
Main Inventor
Yu-Chung Lien
MEDIA MANAGEMENT (17824384)
Main Inventor
Donghua Zhou
INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES (18109830)
Main Inventor
Eric J. Stave
NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS (17827006)
Main Inventor
Kunal R. Parekh
MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER (17826776)
Main Inventor
Shuangqiang Luo
MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804247)
Main Inventor
Fatma Arzum Simsek-Ege
MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804251)
Main Inventor
Fatma Arzum Simsek-Ege
RADIATION HARDENED SEMICONDUCTOR DEVICES AND PACKAGING (17825695)
Main Inventor
Chong Leong Gan
MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING DOPED INTERFACIAL REGIONS, AND RELATED SYSTEMS AND METHODS (17804530)
Main Inventor
Everett A. McTeer
TRANSISTOR WITH GATE ATTACHED FIELD PLATE (17752610)
Main Inventor
Michael A. Smith
TEXTURED OPTOELECTRONIC DEVICES AND ASSOCIATED METHODS OF MANUFACTURE (18359795)
Main Inventor
Lifang Xu
CLOUD-BASED CREATION OF A CUSTOMER-SPECIFIC SYMMETRIC KEY ACTIVATION DATABASE (18448815)
Main Inventor
Lance W. Dover
INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS (17804789)
Main Inventor
Anthony D. Veches
MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804234)
Main Inventor
Fatma Arzum Simsek-Ege
MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES (17804270)
Main Inventor
Fatma Arzum Simsek-Ege
ELECTRONIC DEVICES COMPRISING SEGMENTED HIGH-K DIELECTRIC MATERIALS AND STORAGE NODE MATERIALS, RELATED SYSTEMS, AND METHODS OF FORMING (17804752)
Main Inventor
Yifen Liu
Memory Circuitry And Method Used In Forming Memory Circuitry (17751978)
Main Inventor
Collin Howder
Memory Circuitry And Method Used In Forming Memory Circuitry (17869586)
Main Inventor
Jordan D. Greenlee
Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells ([[US Patent Application 17879140. Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells simplified abstract (Micron Technology, Inc.)|17879140]])
Main Inventor
Adam Barton
METHODS OF FORMING MICROELECTRONIC DEVICES (18359792)
Main Inventor
Collin Howder