View source for 17530971. SELECTIVE METAL RESIDUE AND LINER CLEANSE FOR POST-SUBTRACTIVE ETCH simplified abstract (International Business Machines Corporation)

=SELECTIVE METAL RESIDUE AND LINER CLEANSE FOR POST-SUBTRACTIVE ETCH=


==Organization Name==

[[:Category:International Business Machines Corporation|International Business Machines Corporation]]


[[Category:International Business Machines Corporation]]

==Inventor(s)==

[[:Category:Devika Sarkar Grant of Rensselaer NY (US)|Devika Sarkar Grant of Rensselaer NY (US)]][[Category:Devika Sarkar Grant of Rensselaer NY (US)]]

[[:Category:Somnath Ghosh of Clifton Park NY (US)|Somnath Ghosh of Clifton Park NY (US)]][[Category:Somnath Ghosh of Clifton Park NY (US)]]

==SELECTIVE METAL RESIDUE AND LINER CLEANSE FOR POST-SUBTRACTIVE ETCH - A simplified explanation of the abstract==


This abstract first appeared for US patent application 17530971 titled 'SELECTIVE METAL RESIDUE AND LINER CLEANSE FOR POST-SUBTRACTIVE ETCH

==Simplified Explanation==

The patent application describes structures in semiconductor devices and methods for forming these structures. Here is a simplified explanation of the abstract:

* A hard mask layer is etched to create a patterned hard mask.
* The interconnect layer is etched using the hard mask to create multiple metal lines.
* The hard mask is then removed.
* A portion of the liner layer deposited directly on the dielectric layer is etched, and the remaining portion is deposited between the metal lines and the dielectric layer.

Potential Applications:

* Semiconductor device manufacturing
* Integrated circuit fabrication
* Electronics industry

Problems Solved:

* Efficient patterning of metal lines in semiconductor devices
* Removal of unwanted portions of the liner layer
* Ensuring proper deposition of the liner layer between metal lines and the dielectric layer

Benefits:

* Improved precision and accuracy in creating metal lines
* Enhanced performance and reliability of semiconductor devices
* Cost-effective manufacturing process


==Original Abstract Submitted==

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.



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