SEARCH RESULTS for assignor:"CHENG, KANGGUO"

Showing 1 to 20 of 425 results

Reel/Frame

Last Update:

Patent(s)

(X0) 15997154: CMOS COMPATIBLE FUSE OR RESISTOR USING SELF-ALIGNED CONTACTS

(A1) 20180286856: CMOS COMPATIBLE FUSE OR RESISTOR USING SELF-ALIGNED CONTACTS

Reel/Frame

Last Update:

Patent(s)

(X0) 16000153: VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON A SUBSTRATE WITH VARYING EFFECTIVE GATE LENGTHS

(A1) 20180286980: VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS ON A SUBSTRATE WITH VARYING EFFECTIVE GATE LENGTHS

Reel/Frame

Last Update:

Patent(s)

(X0) 15811830: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

(A1) 20180286978: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

Reel/Frame

Last Update:

Patent(s)

(X0) 15298733: DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER

(A1) 20170213884: DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER

(B2) 1: DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15471416: AIR-GAP TOP SPACER AND SELF-ALIGNED METAL GATE FOR VERTICAL FETS

(A1) 20170330965: AIR-GAP TOP SPACER AND SELF-ALIGNED METAL GATE FOR VERTICAL FETS

(B2) 1: AIR-GAP TOP SPACER AND SELF-ALIGNED METAL GATE FOR VERTICAL FETS

Reel/Frame

Last Update:

Patent(s)

(A1) 20180286977: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

(B2) 1: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

(X0) 15477355: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

(B1) 1: VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

Reel/Frame

Last Update:

Patent(s)

(X0) 15698041: INTEGRATED DEVICE WITH P-I-N DIODES AND VERTICAL FIELD EFFECT TRANSISTORS

(A1) 20180053758: INTEGRATED DEVICE WITH P-I-N DIODES AND VERTICAL FIELD EFFECT TRANSISTORS

(B2) 1: INTEGRATED DEVICE WITH P-I-N DIODES AND VERTICAL FIELD EFFECT TRANSISTORS

Reel/Frame

Last Update:

Patent(s)

(X0) 15863202: FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES

(A1) 20180145270: FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES

(B2) 1: FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES

Reel/Frame

Last Update:

Patent(s)

(X0) 15986031: UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

(A1) 20180277648: UNMERGED EPITAXIAL PROCESS FOR FINFET DEVICES WITH AGGRESSIVE FIN PITCH SCALING

Reel/Frame

Last Update:

Patent(s)

(X0) 15988375: SINGLE-ELECTRON TRANSISTOR WITH SELF-ALIGNED COULOMB BLOCKADE

(A1) 20180277670: SINGLE-ELECTRON TRANSISTOR WITH SELF-ALIGNED COULOMB BLOCKADE

Reel/Frame

Last Update:

Patent(s)

(X0) 15992733: PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH

(A1) 20180277676: PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH

Reel/Frame

Last Update:

Patent(s)

(X0) 15966232: VERTICAL FIELD EFFECT TRANSISTOR WITH IMPROVED RELIABILITY

(A1) 20180277675: VERTICAL FIELD EFFECT TRANSISTOR WITH IMPROVED RELIABILITY

Reel/Frame

Last Update:

Patent(s)

(X0) 15993042: FABRICATION OF VERTICAL FUSES FROM VERTICAL FINS

(A1) 20180277481: FABRICATION OF VERTICAL FUSES FROM VERTICAL FINS

Reel/Frame

Last Update:

Patent(s)

(X0) 15464768: METHOD AND STRUCTURE FOR FORMING IMPROVED SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS

(A1) 20180277669: METHOD AND STRUCTURE FOR FORMING IMPROVED SINGLE ELECTRON TRANSISTOR WITH GAP TUNNEL BARRIERS

Reel/Frame

Last Update:

Patent(s)

(X0) 15468300: VERTICAL FIELD EFFECT TRANSISTOR WITH IMPROVED RELIABILITY

(A1) 20180277674: VERTICAL FIELD EFFECT TRANSISTOR WITH IMPROVED RELIABILITY

Reel/Frame

Last Update:

Patent(s)

(X0) 15470352: NANOSHEET CMOS TRANSISTORS

(A1) 20180277628: NANOSHEET CMOS TRANSISTORS

Reel/Frame

Last Update:

Patent(s)

(X0) 15805700: NANOSHEET CMOS TRANSISTORS

(A1) 20180277630: NANOSHEET CMOS TRANSISTORS

Reel/Frame

Last Update:

Patent(s)

(X0) 15177358: FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN

(A1) 20170358497: FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN

(B2) 1: FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN

Reel/Frame

Last Update:

Patent(s)

(X0) 15688224: METHOD AND STRUCTURE FOR IMPROVING FINFET WITH EPITAXY SOURCE/DRAIN

(A1) 20170358643: METHOD AND STRUCTURE FOR IMPROVING FINFET WITH EPITAXY SOURCE/DRAIN

(B2) 1: METHOD AND STRUCTURE FOR IMPROVING FINFET WITH EPITAXY SOURCE/DRAIN

Reel/Frame

Last Update:

Patent(s)

(X0) 14936069: METHOD AND STRUCTURE OF STACKED FINFET

(A1) 20170133507: METHOD AND STRUCTURE OF STACKED FINFET

(B2) 1: METHOD AND STRUCTURE OF STACKED FINFET