SEARCH RESULTS for assignor:"CHENG, KANGGUO"

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(X0) 14581043: CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

(A1) 20160181352: CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

(B2) 1: CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

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(X0) 14732174: COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

(A1) 20160358905: COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

(B2) 1: COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

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(X0) 15157012: VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT

(A1) 20170338334: VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT

(B2) 1: VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT

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(X0) 15186964: FINFET CMOS WITH SI NFET AND SIGE PFET

(A1) 20170170180: FINFET CMOS WITH SI NFET AND SIGE PFET

(B2) 1: FINFET CMOS WITH SI NFET AND SIGE PFET

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(X0) 15227142: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

(A1) 20170047226: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

(B2) 1: FORMING A CONTACT FOR A TALL FIN TRANSISTOR

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(X0) 15244067: FORMING A GATE CONTACT IN THE ACTIVE AREA

(A1) 20170054004: FORMING A GATE CONTACT IN THE ACTIVE AREA

(B2) 1: FORMING A GATE CONTACT IN THE ACTIVE AREA

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(X0) 15292187: BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

(A1) 20170033103: BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

(B2) 1: BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

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(X0) 15417932: CAPACITORS

(A1) 20170141184: CAPACITORS

(B2) 1: CAPACITORS

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(X0) 15448047: VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT

(A1) 20180254344: VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT

(B2) 1: VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT

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(X0) 15448626: SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION

(A1) 20170179137: SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION

(B2) 1: SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION

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(X0) 15498669: VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

(A1) 20170229449: VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

(B2) 1: VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

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(X0) 15596376: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

(A1) 20180090380: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

(B2) 1: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

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(X0) 15596376: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

(A1) 20180090380: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

(B2) 1: BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

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(X0) 15606736: FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

(A1) 20180006037: FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

(B2) 1: FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

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(X0) 15627875: CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

(A1) 20170287904: CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

(B2) 1: CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

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(X0) 15640766: Stacked Nanowires

(A1) 20170301554: Stacked Nanowires

(B2) 1: Stacked Nanowires

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(X0) 15670001: FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

(A1) 20180019171: FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

(B2) 1: FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

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(X0) 15683351: VERTICAL SCHOTTKY CONTACT FET

(A1) 20180026135: VERTICAL SCHOTTKY CONTACT FET

(B2) 1: VERTICAL SCHOTTKY CONTACT FET

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(X0) 15790037: STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

(A1) 20180069026: STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

(B2) 1: STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

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(X0) 15795445: HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION

(A1) 20180069124: HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION

(B2) 1: HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION