SEARCH RESULTS for assignor:"BAO, TIEN-I"

Showing 1 to 20 of 25 results

Share this

Reel/Frame

Last Update:

Patent(s)

(X0) 16016804: System and Method of Forming a Porous Low-K Structure

(A1) 20180308689: System and Method of Forming a Porous Low-K Structure

Reel/Frame

Last Update:

Patent(s)

(X0) 16017039: COPPER ETCHING INTEGRATION SCHEME

(A1) 20180301416: COPPER ETCHING INTEGRATION SCHEME

Reel/Frame

Last Update:

Patent(s)

(X0) 16006120: SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

(A1) 20180301409: SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Reel/Frame

Last Update:

Patent(s)

(X0) 15016866: SEMICONDUCTOR DEVICE STRUCTURE WITH GRAPHENE LAYER

(A1) 20170229396: SEMICONDUCTOR DEVICE STRUCTURE WITH GRAPHENE LAYER

(B2) 1: SEMICONDUCTOR DEVICE STRUCTURE WITH GRAPHENE LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15820961: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

(A1) 20180096850: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

(B2) 1: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15820961: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

(A1) 20180096850: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

(B2) 1: METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICE HAVING GATE SPACER PROTECTION LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15436147: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

(A1) 20170162435: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

(B2) 1: SEMICONDUCTOR DEVICE INCLUDING A TARGET INTEGRATED CIRCUIT PATTERN

Reel/Frame

Last Update:

Patent(s)

(X0) 15942947: Porogen Bonded Gap Filling Material in Semiconductor Manufacturing

(A1) 20180226293: Porogen Bonded Gap Filling Material in Semiconductor Manufacturing

Reel/Frame

Last Update:

Patent(s)

(X0) 15924549: METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

(A1) 20180211911: METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15912177: Via Connection to a Partially Filled Trench

(A1) 20180197750: Via Connection to a Partially Filled Trench

Reel/Frame

Last Update:

Patent(s)

(X0) 15463617: COPPER ETCHING INTEGRATION SCHEME

(A1) 20170194258: COPPER ETCHING INTEGRATION SCHEME

(B2) 1: COPPER ETCHING INTEGRATION SCHEME

Reel/Frame

Last Update:

Patent(s)

(X0) 14813177: Semiconductor Device Having a Porous Low-K Structure

(A1) 20170033043: Semiconductor Device Having a Porous Low-K Structure

(B2) 1: Semiconductor Device Having a Porous Low-K Structure

Reel/Frame

Last Update:

Patent(s)

(X0) 14524228: SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE PILLAR AND CONDUCTIVE LINE AND METHOD FOR FORMING THE SAME

(A1) 20160118336: SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE PILLAR AND CONDUCTIVE LINE AND METHOD FOR FORMING THE SAME

(B2) 1: SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE PILLAR AND CONDUCTIVE LINE AND METHOD FOR FORMING THE SAME

Reel/Frame

Last Update:

Patent(s)

(X0) 15249805: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

(A1) 20160365276: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

(B2) 9: METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE

Reel/Frame

Last Update:

Patent(s)

(A1) 20180151738: Finfets and Methods of Forming Finfets

(B2) 9: Finfets and Methods of Forming Finfets

(X0) 15455603: Finfets and Methods of Forming Finfets

(B1) 9: Finfets and Methods of Forming Finfets

Reel/Frame

Last Update:

Patent(s)

(X0) 14752097: POROGEN BONDED GAP FILLING MATERIAL IN SEMICONDUCTOR MANUFACTURING

(A1) 20160379874: POROGEN BONDED GAP FILLING MATERIAL IN SEMICONDUCTOR MANUFACTURING

(B2) 9: POROGEN BONDED GAP FILLING MATERIAL IN SEMICONDUCTOR MANUFACTURING

Reel/Frame

Last Update:

Patent(s)

(X0) 15280703: FinFET Cut-Last Process Using Oxide Trench Fill

(A1) 20180090491: FinFET Cut-Last Process Using Oxide Trench Fill

Reel/Frame

Last Update:

Patent(s)

(X0) 15601562: METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

(A1) 20170256486: METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

(B2) 9: METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

Reel/Frame

Last Update:

Patent(s)

(X0) 15810337: Self-Aligned Interconnection Structure and Method

(A1) 20180076132: Self-Aligned Interconnection Structure and Method

Reel/Frame

Last Update:

Patent(s)

(X0) 14715039: METHOD OF FABRICATION POLYMER WAVEGUIDE

(A1) 20150253500: METHOD OF FABRICATION POLYMER WAVEGUIDE

(B2) 9: METHOD OF FABRICATION POLYMER WAVEGUIDE