SEARCH RESULTS for assignee:"UNITY SEMICONDUCTOR CORPORATION"

Showing 1 to 7 of 7 results

Last Update Patent(s) Assignor(s) Orig. Assignee(s) Assignee(s) Reel/Frame
12-Jun-2018

(X0) 1: HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

(A1) 2: HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

(B2) 9: HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

CHEVALLIER, CHRISTOPHE J.

SIAU, CHANG HUA

UNITY SEMICONDUCTOR CORPORATION

45042/289

11-May-2018

(X0) 1: TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

(A1) 2: TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

RINERSON, DARRELL

CHEVALLIER, CHRISTOPHE J.

LAMBERTSON, ROY

KINNEY, WAYNE

SANCHEZ JR, JOHN E.

SCHLOSS, LAWRENCE

SWAB, PHILIP F.S

WARD, EDMOND R

UNITY SEMICONDUCTOR CORPORATION

45765/7

11-May-2018

(X0) 1: MULTI-LAYERED CONDUCTIVE METAL OXIDE STRUCTURES AND METHODS FOR FACILITATING ENHANCED PERFORMANCE CHARACTERISTICS OF TWO-TERMINAL MEMORY CELLS

(A1) 2: MULTI-LAYERED CONDUCTIVE METAL OXIDE STRUCTURES AND METHODS FOR FACILITATING ENHANCED PERFORMANCE CHARACTERISTICS OF TWO-TERMINAL MEMORY CELLS

WU, JIAN

MEYER, RENE

UNITY SEMICONDUCTOR CORPORATION

45765/932

05-Apr-2018

(X0) 1: ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY

(A1) 2: ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY

CHEVALLIER, CHRISTOPHE

SIAU, CHANG HUA

UNITY SEMICONDUCTOR CORPORATION

44732/744

27-Mar-2018

(X0) 1: ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS

(A1) 2: ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS

UNITY SEMICONDUCTOR CORPORATION

45353/39

16-Jan-2018

(X0) 1: CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY

(A1) 2: CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY

(B2) 9: CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY

CHEVALLIER, CHRISTOPHE J.

LIM, SEOW FONG

SIAU, CHANG HUA

UNITY SEMICONDUCTOR CORPORATION

39359/952

16-Jan-2018

(X0) 1: GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

(A1) 2: GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

(B2) 9: GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

SIAU, CHANG HUA

BATEMAN, BRUCE LYNN

UNITY SEMICONDUCTOR CORPORATION

43809/669