SEARCH RESULTS for SOITEC

Recent Patent Assignments Patent Assignments - (Total found: 77)

Patent(s) Assignor(s) Orig. Assignee(s) Assignee(s) Reel/Frame

(X0) 14413405: ANTIFUSE

(A1) 20150171094: ANTIFUSE

HOFMANN, FRANZ

SOITEC

37958/568

(X0) 15159646: METHOD FOR TRANSFERRING A LAYER FROM A SINGLE-CRYSTAL SUBSTRATE

(A1) 20160351438: METHOD FOR TRANSFERRING A LAYER FROM A SINGLE-CRYSTAL SUBSTRATE

ECARNOT, LUDOVIC

DAVAL, NICOLAS

BEN MOHAMED, NADIA

BOEDT, FRANCOIS

DAVID, CAROLE

GUERIN, ISABELLE

SOITEC

41813/343

(X0) 14272660: METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES

(A1) 20150325686: METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES

(B2) 9620626: METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXATION, AND RELATED STRUCTURES

ALLIBERT, FREDERIC

N/A

SOITEC

32849/167

(X0) 15264821: STRUCTURE FOR RADIOFREQUENCY APPLICATIONS AND PROCESS FOR MANUFACTURING SUCH A STRUCTURE

(A1) 20170084478: STRUCTURE FOR RADIOFREQUENCY APPLICATIONS AND PROCESS FOR MANUFACTURING SUCH A STRUCTURE

NGUYEN, BICH-YEN

MALEVILLE, CHRISTOPHE

SOITEC

41235/834

(X0) 13575281: SOLAR CELL ASSEMBLY II

(A1) 20120285530: SOLAR CELL ASSEMBLY II

(B2) 9590126: SOLAR CELL ASSEMBLY II

ZIEGLER, MARTIN

VAN RIESEN, SASCHA

N/A

SOITEC SOLAR GMBH

28786/830

(X0) 14686229: METHOD FOR TRANSFERRING A USEFUL LAYER

(A1) 20150303098: METHOD FOR TRANSFERRING A USEFUL LAYER

(B2) 9589830: METHOD FOR TRANSFERRING A USEFUL LAYER

LANDRU, DIDIER

KONONCHUK, OLEG

BEN MOHAMED, NADIA

N/A

SOITEC

36535/712

(X0) 14782548: ADVANCED THERMALLY COMPENSATED SURFACE ACOUSTIC WAVE DEVICE AND FABRICATION

(A1) 20160065162: ADVANCED THERMALLY COMPENSATED SURFACE ACOUSTIC WAVE DEVICE AND FABRICATION

ZINCK, CHRISTOPHE

DESBONNETS, ERIC

SOITEC

41105/319

(X0) 14411741: METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING

(A1) 20150179603: METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING

RADU, IONUT

BROEKAART, MARCEL

CASTEX, ARNAUD

GAUDIN, GWELTAZ

RIOU, GREGORY

SOITEC

41078/660

(X0) 14377738: METHOD FOR TRANSFERRING A LAYER COMPRISING A COMPRESSIVE STRESS LAYER AND RELATED STRUCTURES

(A1) 20150364364: METHOD FOR TRANSFERRING A LAYER COMPRISING A COMPRESSIVE STRESS LAYER AND RELATED STRUCTURES

(B2) 9548237: METHOD FOR TRANSFERRING A LAYER COMPRISING A COMPRESSIVE STRESS LAYER AND RELATED STRUCTURES

GAUDIN, GWELTAZ

KONONCHUK, OLEG

RADU, IONUT

N/A

SOITEC

34779/462

(X0) 14434624: METHOD FOR BONDING BY MEANS OF MOLECULAR ADHESION

(A1) 20150235851: METHOD FOR BONDING BY MEANS OF MOLECULAR ADHESION

(B2) 9548202: METHOD FOR BONDING BY MEANS OF MOLECULAR ADHESION

BROEKAART, MARCEL

CASTEX, ARNAUD

N/A

SOITEC

36394/152

(X0) 14361265: APPARATUS FOR THE INDUSTRIAL PRODUCTION OF PHOTOVOLTAIC CONCENTRATOR MODULES

(A1) 20140331472: APPARATUS FOR THE INDUSTRIAL PRODUCTION OF PHOTOVOLTAIC CONCENTRATOR MODULES

LANGE, GERRIT

HAARBURGER, KARL FRIEDRICH

GERSTER, ECKART

SOITEC SOLAR GMBH

33875/745

(X0) 13288396: GALLIUM TRICHLORIDE INJECTION SCHEME

(A1) 20120048182: GALLIUM TRICHLORIDE INJECTION SCHEME

(B2) 8323407: GALLIUM TRICHLORIDE INJECTION SCHEME

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES

N/A

SOITEC

34013/614

(X0) 14350435: MULTI JUNCTIONS IN A SEMICONDUCTOR DEVICE FORMED BY DIFFERENT DEPOSITION TECHNIQUES

(A1) 20140261653: MULTI JUNCTIONS IN A SEMICONDUCTOR DEVICE FORMED BY DIFFERENT DEPOSITION TECHNIQUES

KRAUSE, RAINER

GHYSELEN, BRUNO

SOITEC

34042/489

(X0) 14233685: ACTIVE COOLING FOR A CONCENTRATED PHOTOVOLTAIC CELL

(A1) 20140144486: ACTIVE COOLING FOR A CONCENTRATED PHOTOVOLTAIC CELL

KRAUSE, RAINER

GHYSELEN, BRUNO

SOITEC

34042/900

(X0) 13966921: TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER

(A1) 20130327266: TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER

(B2) 8887650: TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER

ARENA, CHANTAL

WERKHOVEN, CHRISTIAAN

N/A

SOITEC

31012/17

(X0) 13422697: SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER

(A1) 20120243360: SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER

(B2) 9159400: SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED WITH A LOCAL COLUMN DECODER

FERRANT, RICHARD

ENDERS, GERHARD

MAZURE, CARLOS

N/A

SOITEC

28307/716

(X0) 13254729: ETCHING COMPOSITION, IN PARTICULAR FOR SILICON MATERIALS, METHOD FOR CHARACTERIZING DEFECTS ON SURFACES OF SUCH MATERIALS AND PROCESS OF TREATING SUCH SURFACES WITH THE ETCHING COMPOSTION

(A1) 20120094501: ETCHING COMPOSITION, IN PARTICULAR FOR SILICON MATERIALS, METHOD FOR CHARACTERIZING DEFECTS ON SURFACES OF SUCH MATERIALS AND PROCESS OF TREATING SUCH SURFACES WITH THE ETCHING COMPOSTION

MAEHLISS, JOCHEN

KOLBESEN, BERND

HAKIM, ROMANA

BRUNIER, FRANCOIS

SOITEC

28326/6

(X0) 13495632: PSEUDO-INVERTER CIRCUIT ON SeOI

(A1) 20120250444: PSEUDO-INVERTER CIRCUIT ON SeOI

(B2) 8654602: PSEUDO-INVERTER CIRCUIT ON SeOI

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES

N/A

SOITEC

28458/501

(X0) 15036030: METHOD FOR TESTING A CONCENTRATED PHOTOVOLTAIC MODULE

(A1) 20160344340: METHOD FOR TESTING A CONCENTRATED PHOTOVOLTAIC MODULE

BLANCHARD, REMI

GASTALDO, PHILIPPE

SOITEC SOLAR GMBH

38553/962

(X0) 13680241: GALLIUM TRICHLORIDE INJECTION SCHEME

(A1) 20130104802: GALLIUM TRICHLORIDE INJECTION SCHEME

(B2) 9481943: GALLIUM TRICHLORIDE INJECTION SCHEME

ARENA, CHANTAL

WERKHOVEN, CHRISTIAAN

N/A

SOITEC

29319/337

(X0) 13828585: GAS INJECTORS INCLUDING A FUNNEL- OR WEDGE-SHAPED CHANNEL FOR CHEMICAL VAPOR DEPOSITION (CVD) SYSTEMS AND CVD SYSTEMS WITH THE SAME

(A1) 20130199441: GAS INJECTORS INCLUDING A FUNNEL- OR WEDGE-SHAPED CHANNEL FOR CHEMICAL VAPOR DEPOSITION (CVD) SYSTEMS AND CVD SYSTEMS WITH THE SAME

(B2) 9481944: GAS INJECTORS INCLUDING A FUNNEL- OR WEDGE-SHAPED CHANNEL FOR CHEMICAL VAPOR DEPOSITION (CVD) SYSTEMS AND CVD SYSTEMS WITH THE SAME

ARENA, CHANTAL

BERTRAM, RONALD THOMAS, JR.

LINDOW, ED

WERKHOVEN, CHRISTIAAN

N/A

SOITEC

31147/767

(X0) 14416825: METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES

(A1) 20150191344: METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES

(B2) 9481566: METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES

SADAKA, MARIAM

BLANCHARD, CHRYSTELLE LAGAHE

ASPAR, BERNARD

N/A

SOITEC

34800/988

(X0) 14346270: PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

(A1) 20140225648: PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

(B2) 9496877: PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

MAZURE, CARLOS

NGUYEN, BICH-YEN

FERRANT, RICHARD

N/A

SOITEC

40184/17

8252664: FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL

8507361: FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL

8991673: SUBSTRATE CUTTING DEVICE AND METHOD

8216368: METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER

8541290: OPTOELECTRONIC SUBSTRATE AND METHODS OF MAKING SAME

8183128: METHOD OF REDUCING ROUGHNESS OF A THICK INSULATING LAYER

9011598: METHOD FOR MAKING A COMPOSITE SUBSTRATE AND COMPOSITE SUBSTRATE ACCORDING TO THE METHOD

8349703: METHOD OF BONDING TWO SUBSTRATES

8324078: METHOD AND INSTALLATION FOR FRACTURING A COMPOSITE SUBSTRATE ALONG AN EMBRITTLEMENT PLANE

8492244: METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTURES FABRICATED THEREBY

8241998: METHOD OF PRODUCING AN SOI STRUCTURE WITH AN INSULATING LAYER OF CONTROLLED THICKNESS

8247309: CONTROLLED TEMPERATURE IMPLANTATION

8343850: PROCESS FOR FABRICATING A SUBSTRATE COMPRISING A DEPOSITED BURIED OXIDE LAYER

8198628: DOPED SUBSTRATE TO BE HEATED

8372733: METHOD FOR FABRICATING A LOCALLY PASSIVATED GERMANIUM-ON-INSULATOR SUBSTRATE

8802539: CHARGE RESERVOIR STRUCTURE

8679250: METHOD OF MANUFACTURING A STRUCTURE COMPRISING A SUBSTRATE AND A LAYER DEPOSITED ON ONE OF ITS FACES

8420500: METHOD OF PRODUCING A STRUCTURE BY LAYER TRANSFER

8389380: METHOD FOR MAKING A SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH AN INTEGRATED GROUND PLANE

8324530: METHOD FOR HEATING A WAFER BY MEANS OF A LIGHT FLUX

8455938: DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR

8223582: PSEUDO-INVERTER CIRCUIT ON SeOI

9035474: METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

8263475: METHOD FOR MANUFACTURING HETEROSTRUCTURES

8575010: METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE

8358552: NANO-SENSE AMPLIFIER

8299485: SUBSTRATES FOR MONOLITHIC OPTICAL CIRCUITS AND ELECTRONIC CIRCUITS

8575697: SRAM-TYPE MEMORY CELL

8216917: METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR TYPE SUBSTRATE

8283673: METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE

9063043: ETCHING COMPOSITION, IN PARTICULAR FOR STRAINED OR STRESSED SILICON MATERIALS, METHOD FOR CHARACTERIZING DEFECTS ON SURFACES OF SUCH MATERIALS AND PROCESS OF TREATING SUCH SURFACES WITH THE ETCHING COMPOSITION

8304345: GERMANIUM LAYER POLISHING

8679944: PROGRESSIVE TRIMMING METHOD

8343782: SEMICONDUCTOR DEVICE HAVING AN INGAN LAYER

9275888: TEMPORARY SUBSTRATE, TRANSFER METHOD AND PRODUCTION METHOD

8475612: METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT

8790992: LOW-TEMPERATURE BONDING PROCESS

8429960: PROCESS FOR MEASURING AN ADHESION ENERGY, AND ASSOCIATED SUBSTRATES

8338266: METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE

8305803: DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR

8367521: MANUFACTURE OF THIN SILICON-ON-INSULATOR (SOI) STRUCTURES

8357587: METHOD FOR ROUTING A CHAMFERED SUBSTRATE

8314007: PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESS

8664712: FLASH MEMORY CELL ON SEOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER

8384425: ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE

8304833: MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER

8325506: DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY

8912081: STIFFENING LAYERS FOR THE RELAXATION OF STRAINED LAYERS

8432216: DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER

8372728: PROCESS FOR FABRICATING A MULTILAYER STRUCTURE WITH TRIMMING USING THERMO-MECHANICAL EFFECTS

8431419: UV ABSORPTION BASED MONITOR AND CONTROL OF CHLORIDE GAS STREAM

9490264: DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BURIED INSULATING LAYER, AND PROCESS FOR FABRICATING SAID DEVICE

8508289: DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER

8324072: PROCESS FOR LOCALLY DISSOLVING THE OXIDE LAYER IN A SEMICONDUCTOR-ON-INSULATOR TYPE STRUCTURE

9018678: METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE

8623740: METHOD OF DETACHING SEMI-CONDUCTOR LAYERS AT LOW TEMPERATURE

8513092: METHOD FOR PRODUCING A STACK OF SEMI-CONDUCTOR THIN FILMS

8202785: SURFACE TREATMENT FOR MOLECULAR BONDING

8241942: METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR

8309426: METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES

8357589: METHOD OF THINNING A STRUCTURE

9048288: METHOD FOR TREATING A PART MADE FROM A DECOMPOSABLE SEMICONDUCTOR MATERIAL

8475693: METHODS OF MAKING SUBSTRATE STRUCTURES HAVING A WEAKENED INTERMEDIATE LAYER

8389412: FINISHING METHOD FOR A SILICON ON INSULATOR SUBSTRATE

8575002: DIRECT BONDING METHOD WITH REDUCTION IN OVERLAY MISALIGNMENT

8778777: METHOD FOR MANUFACTURING A HETEROSTRUCTURE AIMING AT REDUCING THE TENSILE STRESS CONDITION OF A DONOR SUBSTRATE

8754505: METHOD OF PRODUCING A HETEROSTRUCTURE WITH LOCAL ADAPTATION OF THE THERMAL EXPANSION COEFFICIENT

8563399: DETACHABLE SUBSTRATE AND PROCESSES FOR FABRICATING AND DETACHING SUCH A SUBSTRATE

8580654: METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES

9224704: PROCESS FOR REALIZING A CONNECTING STRUCTURE

8962492: METHOD TO THIN A SILICON-ON-INSULATOR SUBSTRATE

8420506: PROCESS FOR CLEAVING A SUBSTRATE

8492844: FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER

8492877: SEMICONDUCTOR STRUCTURE WITH SMOOTHED SURFACE AND PROCESS FOR OBTAINING SUCH A STRUCTURE

8497190: PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE

8382898: METHODS FOR HIGH VOLUME MANUFACTURE OF GROUP III-V SEMICONDUCTOR MATERIALS

8585820: ABATEMENT OF REACTION GASES FROM GALLIUM NITRIDE DEPOSITION

8197597: GALLIUM TRICHLORIDE INJECTION SCHEME

8574968: EPITAXIAL METHODS AND TEMPLATES GROWN BY THE METHODS

8236593: METHODS FOR IMPROVING THE QUALITY OF EPITAXIALLY-GROWN SEMICONDUCTOR MATERIALS

8318612: METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS

8545628: TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER

9175419: APPARATUS FOR DELIVERING PRECURSOR GASES TO AN EPITAXIAL GROWTH SUBSTRATE

8388755: THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS

8247314: METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS

8329565: METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS

7888235: FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL

7265029: FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL

7081399: METHOD FOR PRODUCING A HIGH QUALITY USEFUL LAYER ON A SUBSTRATE

8083115: SUBSTRATE CUTTING DEVICE AND METHOD

7182234: SUBSTRATE CUTTING DEVICE AND METHOD

7217639: METHOD OF MANUFACTURING A MATERIAL COMPOUND WAFER

7601217: METHOD OF FABRICATING AN EPITAXIALLY GROWN LAYER

7537949: OPTOELECTRONIC SUBSTRATE AND METHODS OF MAKING SAME

8012289: METHOD OF FABRICATING A RELEASE SUBSTRATE

7544265: METHOD OF FABRICATING A RELEASE SUBSTRATE

7887936: SUBSTRATE WITH DETERMINATE THERMAL EXPANSION COEFFICIENT

7446019: METHOD OF REDUCING ROUGHNESS OF A THICK INSULATING LAYER

7939387: PATTERNED THIN SOI

7645682: BONDING INTERFACE QUALITY BY COLD CLEANING AND HOT BONDING

8048693: METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS

7981767: METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTURES FABRICATED THEREBY

8093077: METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE

8062564: METHOD OF PRODUCING A PLATE-SHAPED STRUCTURE, IN PARTICULAR, FROM SILICON, USE OF SAID METHOD AND PLATE-SHAPED STRUCTURE THUS PRODUCED, IN PARTICULAR FROM SILICON

7235427: METHOD FOR TREATING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY SAID METHOD

6902988: METHOD FOR TREATING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY SAID METHOD

6936523: TWO-STAGE ANNEALING METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATES

7645392: METHODS FOR PREPARING A BONDING SURFACE OF A SEMICONDUCTOR WAFER

7749862: METHODS FOR MINIMIZING DEFECTS WHEN TRANSFERRING A SEMICONDUCTOR USEFUL LAYER

8323407: GALLIUM TRICHLORIDE INJECTION SCHEME

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES

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SOITEC

27800/911

(X0) 15153509: CALIBRATION METHOD FOR HEAT TREATMENT UNITS

(A1) 20160336215: CALIBRATION METHOD FOR HEAT TREATMENT UNITS

MOUGEL, SEBASTIEN

MASSELIN, DIDIER

SOITEC

39530/788

(X0) 14780473: ADVANCED CPV SOLAR CELL ASSEMBLY PROCESS

(A1) 20160056318: ADVANCED CPV SOLAR CELL ASSEMBLY PROCESS

AULNETTE, CÉCILE

KRAUSE, RAINER

GUIOT, ERIC

MAZALEYRAT, ERIC

DRAZEK, CHARLOTTE

SOITEC

39616/251

(X0) 14424311: METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTERFACE

(A1) 20150221544: METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTERFACE

(B2) 9437473: METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTERFACE

LANDRU, DIDIER

FIGUET, CHRISTOPHE

N/A

SOITEC

35643/560

(X0) 14761471: BACK GATE IN SELECT TRANSISTOR FOR EDRAM

(A1) 20150357333: BACK GATE IN SELECT TRANSISTOR FOR EDRAM

ENDERS, GERHARD

SOITEC

39741/199

(X0) 14903961: METHOD FOR LOCATING DEVICES

(A1) 20160197006: METHOD FOR LOCATING DEVICES

BROEKAART, MARCEL

BLANCHARD, CHRYSTELLE LAGAHE

RADU, IONUT

SOITEC

39768/748

(X0) 14947254: ASSEMBLY PROCESS OF TWO SUBSTRATES

(A1) 20160152017: ASSEMBLY PROCESS OF TWO SUBSTRATES

LANDRU, DIDIER

DELAGE, CAPUCINE

SOITEC

39834/73

(X0) 15078902: METHOD FOR REDUCING THE METAL CONTAMINATION ON A SURFACE OF A SUBSTRATE

(A1) 20160284608: METHOD FOR REDUCING THE METAL CONTAMINATION ON A SURFACE OF A SUBSTRATE

BARGE, THIERRY

SOITEC

39530/796

(X0) 14380312: MULTIPLEXER, LOOK-UP TABLE AND FPGA

(A1) 20150028920: MULTIPLEXER, LOOK-UP TABLE AND FPGA

FERRANT, RICHARD

SOITEC

39897/26

(X0) 15083725: PROCESS FOR FABRICATING A STRUCTURE HAVING A BURIED DIELECTRIC LAYER OF UNIFORM THICKNESS

(A1) 20160293476: PROCESS FOR FABRICATING A STRUCTURE HAVING A BURIED DIELECTRIC LAYER OF UNIFORM THICKNESS

DAVID, CAROLE

COCCHI, ANNE-SOPHIE

SOITEC

38731/477

(X0) 15088432: ADVANCED SOLID ELECTROLYTE AND METHOD OF FABRICATION

(A1) 20160293989: ADVANCED SOLID ELECTROLYTE AND METHOD OF FABRICATION

GHYSELEN, BRUNO

SOITEC

39530/559

(X0) 14777225: FINFET WITH BACK-GATE

(A1) 20160020326: FINFET WITH BACK-GATE

MAZURE, CARLOS

HOFMANN, FRANZ

SOITEC

40000/504

(X0) 13629093: PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE

(A1) 20130207244: PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE

(B2) 9230848: PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE

DAVID, CAROLE

KERDILES, SEBASTIEN

N/A

SOITEC

29213/146

(X0) 14385436: EPROM CELL

(A1) 20150042381: EPROM CELL

(B2) 9230662: EPROM CELL

FERRANT, RICHARD

N/A

SOITEC

35804/547

(X0) 14426509: METHOD OF DETACHING A LAYER

(A1) 20150243551: METHOD OF DETACHING A LAYER

BARTHELEMY, ALEXANDRE

SOITEC

37410/75

(X0) 14768976: PHOTOACTIVE DEVICES HAVING LOW BANDGAP ACTIVE LAYERS CONFIGURED FOR IMPROVED EFFICIENCY AND RELATED METHODS

(A1) 20160005909: PHOTOACTIVE DEVICES HAVING LOW BANDGAP ACTIVE LAYERS CONFIGURED FOR IMPROVED EFFICIENCY AND RELATED METHODS

NEWMAN, FRED

SOITEC

37468/396

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