SEARCH RESULTS for assignee:"spin transfer technologies"

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(X0) 15916050: MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME

(A1) 20190280193: MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME

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(B2) 10388861: MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME

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(X0) 15916078: MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME

(A1) 20190280194: MAGNETIC TUNNEL JUNCTION WAFER ADAPTOR USED IN MAGNETIC ANNEALING FURNACE AND METHOD OF USING THE SAME

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(X0) 15865066: FABRICATION OF A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ) USING BLOCK COPOLYMERS

(A1) 20190214551: FABRICATION OF A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ) USING BLOCK COPOLYMERS

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(B2) 10333063: FABRICATION OF A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ) USING BLOCK COPOLYMERS

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(X0) 15865135: Dual Threshold Voltage Devices

(A1) 20190214431: Dual Threshold Voltage Devices

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(X0) 15865118: HIGH DENSITY 3D MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL INTEGRATION USING WAFER CUT AND TRANSFER

(A1) 20190214552: HIGH DENSITY 3D MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL INTEGRATION USING WAFER CUT AND TRANSFER

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(X0) 15866381: DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

(A1) 20190214432: DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

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(X0) 15866381: DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

(A1) 20190214432: DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

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(X0) 15866394: METHOD FOR MANUFACTURING A MAGNETIC MEMORY ELEMENT ARRAY USING HIGH ANGLE SIDE ETCH TO OPEN TOP ELECTRICAL CONTACT

(A1) 20190214553: METHOD FOR MANUFACTURING A MAGNETIC MEMORY ELEMENT ARRAY USING HIGH ANGLE SIDE ETCH TO OPEN TOP ELECTRICAL CONTACT

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(X0) 15865249: DEVICES INCLUDING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS

(A1) 20190214429: DEVICES INCLUDING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS

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(X0) 15862788: PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH SKYRMIONIC ENHANCEMENT LAYERS FOR THE PRECESSIONAL SPIN CURRENT MAGNETIC LAYER

(A1) 20190214548: PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH SKYRMIONIC ENHANCEMENT LAYERS FOR THE PRECESSIONAL SPIN CURRENT MAGNETIC LAYER

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(X0) 15865144: Dual Gate Memory Devices

(A1) 20190214069: Dual Gate Memory Devices

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(X0) 15865247: METHODS OF FABRICATING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS

(A1) 20190214430: METHODS OF FABRICATING MAGNETIC TUNNEL JUNCTIONS INTEGRATED WITH SELECTORS

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(X0) 15855660: SHARED BIT LINE ARRAY ARCHITECTURE FOR MAGNETORESISTIVE MEMORY

(A1) 20190198078: SHARED BIT LINE ARRAY ARCHITECTURE FOR MAGNETORESISTIVE MEMORY

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(X0) 15855757: Magnetic Field Transducer Mounting Apparatus for MTJ Device Testers

(A1) 20190195914: Magnetic Field Transducer Mounting Apparatus for MTJ Device Testers

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(X0) 15855886: FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO SHORT DURING TESTING AND USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES TO CORRECT THEM

(A1) 20190121693: FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO SHORT DURING TESTING AND USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES TO CORRECT THEM

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(X0) 15855866: FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS OF ACCEPTABLE HIGH AND LOW RESISTIVE BITS THEREBY LOWERING THE MARGIN AND INCREASING THE SPEED OF THE SENSE AMPLIFIERS

(A1) 20190121692: FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS OF ACCEPTABLE HIGH AND LOW RESISTIVE BITS THEREBY LOWERING THE MARGIN AND INCREASING THE SPEED OF THE SENSE AMPLIFIERS

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(X0) 15855910: OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") MEMORY DEVICE AND CORRECTING FAILURE BITS THEREFROM BY USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES

(A1) 20190121694: OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") MEMORY DEVICE AND CORRECTING FAILURE BITS THEREFROM BY USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES

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(X0) 16197622: Spin Transfer Torque Structure for MRAM Devices Having a Spin Current Injection Capping Layer

(A1) 20190109278: Spin Transfer Torque Structure for MRAM Devices Having a Spin Current Injection Capping Layer

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(X0) 15445260: PRECESSIONAL SPIN CURRENT STRUCTURE FOR MRAM

(A1) 20180248113: PRECESSIONAL SPIN CURRENT STRUCTURE FOR MRAM

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(X0) 15445362: PRECESSIONAL SPIN CURRENT STRUCTURE FOR MRAM

(A1) 20180248110: PRECESSIONAL SPIN CURRENT STRUCTURE FOR MRAM