Taiwan semiconductor manufacturing co., ltd. (20240160820). Attribute-Point-Based Timing Constraint Formal Verification simplified abstract

Attribute-Point-Based Timing Constraint Formal Verification

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Chao-Chun Lo of Hsinchu (TW)

Boh-Yi Huang of San Jose CA (US)

Chih-yuan Stephen Yu of San Jose CA (US)

Attribute-Point-Based Timing Constraint Formal Verification - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240160820 titled 'Attribute-Point-Based Timing Constraint Formal Verification

Simplified Explanation

The patent application describes systems and methods for attribute-point-based timing formal verification of ASIC and SoC designs.

• Key clock-pin-net-load-setting attributes are extracted from netlists and timing constraints of a target circuit design.
• Clock-pin-net-load-setting attribute mismatch is checked between the target circuit design and a golden circuit design.
• The attribute mismatch is provided for further design or timing constraint modifications and updates.

Potential Applications

This technology can be applied in the semiconductor industry for verifying the timing of ASIC and SoC designs.

Problems Solved

1. Efficient design timing sign-off based on ported netlists and synthesis design constraints. 2. Ensuring accurate timing constraints for complex circuit designs.

Benefits

1. Improved accuracy in timing verification. 2. Streamlined design process. 3. Enhanced reliability of ASIC and SoC designs.

Potential Commercial Applications

"Timing Formal Verification for ASIC and SoC Designs: Commercial Applications"

Possible Prior Art

There may be prior art related to timing verification methods in the semiconductor industry.

Unanswered Questions

1. How does this technology compare to existing timing verification tools in terms of accuracy and efficiency? 2. Are there any limitations or constraints when applying this attribute-point-based timing formal verification method to different types of circuit designs?

Original Abstract Submitted

systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (asic) and system on chip (soc) designs. a target circuit design having a first set of netlists and timing constraints is received. a plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. the clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (sta). the attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (sdc).