Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on November 14th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on November 14th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 362 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (108), H01L29/06 (75), H01L29/423 (72), H01L21/768 (64), H01L29/78 (60) H01L29/42392 (9), H01L23/5226 (7), H01L29/401 (7), H01L29/78618 (6), H01L29/78696 (6)
With keywords such as: layer, structure, semiconductor, dielectric, substrate, gate, region, device, forming, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Hsuan-Ying MAI of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chun LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Kuang CHEN of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Hung FENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B01D35/06, B01D35/30, B03C1/28, B03C1/30
CPC Code(s): B01D35/06
Abstract: a filter is used for removing metallic contaminants in a solvent used in microcircuit fabrication. the filter includes a filter housing including a filter membrane for filtering solvent including metallic contaminants, and a magnet arranged about the filter housing and configured to generate a magnetic field to attract the metallic contaminants prior to the metallic contaminants entering the filter membrane. the magnet is arranged such that the magnetic field of the magnet is greater in a periphery of the filter housing compared to a central portion of the filter housing.
Inventor(s): Yan-Jie Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B06B1/02
CPC Code(s): B06B1/0292
Abstract: a method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.
Inventor(s): Chun-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chu Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B24B7/22, B24B37/04, B24B37/08, B24B49/12
CPC Code(s): B24B7/228
Abstract: a method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. the first polishing process stops on a first layer of the composite carrier. a second polishing process is performed to remove the first layer of the composite carrier. the second polishing process stops on a second layer of the composite carrier. a third polishing process is performed to remove a plurality of layers in the composite carrier. the plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.
Inventor(s): Yi-Chu WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B25B11/00, B23K1/00, B23K37/04
CPC Code(s): B25B11/005
Abstract: a die bonding system includes a pick-and-placer, a carrier fixing platform and a transfer platform. the pick-and-placer includes a suction head for picking up a die and placing the die on a carrier. the carrier fixing platform is used to fix the carrier. the carrier has a bearing surface arranged to face downward or to be inclined at an angle relative to a horizontal plane. the transfer platform includes a driver, the pick-and-placer is arranged on the transfer platform, and the driver controls the pick-and-placer to move to a location under the carrier or tilt the angle relative to the horizontal plane, and the pick-and-placer bonds the die to the bearing surface of the carrier from a location under the carrier or at the angle of tilt.
Inventor(s): Ting-Jung Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B3/00, B81C1/00
CPC Code(s): B81B3/0021
Abstract: various embodiments of the present disclosure are directed towards a semiconductor device. the semiconductor device comprises a substrate. a cavity is disposed in the substrate. a microelectromechanical system (mems) layer is disposed over the substrate. the mems layer comprises a movable diaphragm disposed over the cavity. the movable diaphragm comprises a central region and a peripheral region. the movable diaphragm is flat in the central region of the movable diaphragm. the movable diaphragm is corrugated in the peripheral region of the movable diaphragm.
Inventor(s): Wei-Jhih Mao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Ying Tsai of Pingzhen City (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Sung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wen Cheng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B3/00, B81B7/00
CPC Code(s): B81B3/0051
Abstract: various embodiments of the present disclosure are directed towards an integrated chip (ic) including a substrate. a plurality of adhesive structures is disposed on the substrate. a microelectromechanical systems (mems) structure is disposed on the adhesive structures. the mems structure comprises a movable element disposed within a cavity. a first plurality of stopper bumps is disposed between the movable element and the substrate.
Inventor(s): Wen-Chuan Tai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Fu Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ming Hung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., I-Hsuan Chiu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Fan Hu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81C1/00, B81B3/00
CPC Code(s): B81C1/00801
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. an upper dielectric structure overlies the interconnect structure. a microelectromechanical system (mems) substrate overlies the upper dielectric structure. a cavity is defined between the mems substrate and the upper dielectric structure. the mems substrate comprises a movable membrane over the cavity. a cavity electrode is disposed in the upper dielectric structure and underlies the cavity. a plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. a dielectric protection layer is disposed along a top surface of the cavity electrode. the dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
Inventor(s): Yen-hao CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C08L25/14, C08L33/08, C08L33/14, G03F7/004, G03F7/038, G03F7/20, G03F7/40
CPC Code(s): C08L25/14
Abstract: method of manufacturing semiconductor device includes forming photoresist layer over substrate. photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. photoresist composition includes photoactive compound, crosslinker, copolymer. the copolymer is
Inventor(s): Yen-hao CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C08L25/14, C08L33/08, C08L33/14, G03F7/004, G03F7/038, G03F7/20, G03F7/40
CPC Code(s): C08L25/14
Abstract:
Inventor(s): Tsung-Cheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Ying WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsien LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/455, C23C16/458, H01J37/32
CPC Code(s): C23C16/45536
Abstract: an assembly includes a cover ring having a first surface and a second surface opposite the first surface, the first surface of the cover ring having a first roughness, and a deposition ring having a first surface facing the cover ring and a second surface opposite the first surface, the first surface of the deposition ring having a second roughness. the first roughness is different from the second roughness.
Inventor(s): Chung-Liang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/52, C23C16/455, C23C16/458, G05B13/04, H01L21/02
CPC Code(s): C23C16/52
Abstract: a thin-film deposition system deposits thin films on semiconductor wafers. the thin-film deposition system includes a machine learning based analysis model. the analysis model dynamically selects process conditions for a next deposition process by receiving static process conditions and target thin-film data. the analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted thin-film data that matches the target thin-film data. the deposition system then uses the static and dynamic process conditions data for the next thin-film deposition process.
Inventor(s): Tz-Shian CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01K11/125, H01L21/66, H01L21/67
CPC Code(s): G01K11/125
Abstract: a temperature measuring apparatus for measuring a temperature of a substrate is described. a light emitting source that emits light signals such as laser pulses are applied to the substrate. a detector on the other side of the light emitting source receives the reflected laser pulses. the detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. the temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. to improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a s polarization. the angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.
Inventor(s): Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Wei Su of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Tsun Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wen Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N27/414, G01N27/02, G01N33/543
CPC Code(s): G01N27/4145
Abstract: various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. in some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. further, a first gate electrode and a second gate electrode underlie the substrate. the first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. an interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. a passivation layer is over the substrate and defines a first well and a second well. the first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. in some embodiments, sensing probes are in the first well, but not the second well.
Inventor(s): Jun-Hao DENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ching LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Wen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chi CHIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N29/44, B08B3/04, B08B5/02, B08B13/00, G01B17/00, G01B17/02, G01B21/16, H01L21/02, H01L21/288, H01L21/66, H01L21/67
CPC Code(s): G01N29/44
Abstract: methods and systems disclosed herein use acoustic energy to determine a gap between a wafer and an integrated circuit (ic) processing system and/or determine a thickness of a material layer of the wafer during ic processing implemented by the ic processing system. an exemplary method includes emitting acoustic energy through a substrate and a material layer disposed thereover. the substrate is positioned within an ic processing system. the method further includes receiving reflected acoustic energy from a surface of the substrate and a surface of the material layer disposed thereover and converting the reflected acoustic energy into electrical signals. the electrical signals indicate a thickness of the material layer.
Inventor(s): Chi-Chang LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Yi TANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mill-Jer WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R29/10, G01R31/28
CPC Code(s): G01R29/105
Abstract: a testing device for testing an antenna is provided. the testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. the receiving module includes a substrate, a coupling radiation element disposed on the substrate, and a support disposed on the substrate. the coupling radiation element includes a coupling portion and a first branch connecting to the coupling portion.
Inventor(s): Chia-Ning Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chen Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih Wei Liang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/12
CPC Code(s): G02B6/122
Abstract: optical devices and methods of manufacture with individually tailored lens are presented. in some embodiments the optical device comprises a first substrate, a first lens on a first side of the first substrate, the first lens having a first radius of curvature, and a second lens on the first side of the first substrate, the second lens having a second radius of curvature different from the first radius of curvature.
Inventor(s): Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/122, G02B6/12, G02B6/132, G02B6/136
CPC Code(s): G02B6/1223
Abstract: a semiconductor structure including a semiconductor waveguide layer over a second dielectric layer and between sidewalls of a first dielectric layer. a first cladding layer is between the sidewalls of the first dielectric layer and directly over the semiconductor waveguide layer. a second cladding layer is between sidewalls of the second dielectric layer and directly under the semiconductor waveguide layer. a difference between a refractive index of the semiconductor waveguide layer and a refractive index of the first cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the first dielectric layer. a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second dielectric layer.
Inventor(s): Weiwei Song of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Chih-Chang LIN of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Stefan RUSU of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Min-Hsiang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/124, B29D11/00, G02B6/12, G02B6/122, G02B6/132
CPC Code(s): G02B6/124
Abstract: methods of fabricating optical devices with high refractive index materials are disclosed. the method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. a material of the patterned template layer has a first refractive index. the method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. the waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
Inventor(s): Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/13, G02B6/12, G02B6/124, H01L21/56, H01L23/00, H01L23/48, H01L23/528
CPC Code(s): G02B6/13
Abstract: a packaged device includes an optical ic having an optical feature therein. an interconnect structure including layers of conductive features embedded within respective layers of dielectric materials overlie the optical feature. the interconnect structure is patterned to remove the interconnect structure from over the optical feature and a dielectric material having optically neutral properties, relative to a desired light wavelength(s) is formed over the optical feature. one or more electronic ics may be bonded to the optical ic to form an integrated package.
Inventor(s): Min-Hsiang HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu JOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Cheng-Tse TANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Jr HUNG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Lan-Chou CHO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/30
CPC Code(s): G02B6/305
Abstract: disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. in one embodiment, a semiconductor device for optical coupling is disclosed. the semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. the plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. the plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L27/146
CPC Code(s): G02B6/4206
Abstract: a method includes forming a package, which includes an optical die and a protection layer attached to the optical die. the optical die includes a micro lens, with the protection layer and the micro lens being on a same side of the optical die. the method further includes encapsulating the package in an encapsulant, planarizing the encapsulant to reveal the protection layer, and removing the protection layer to form a recess in the encapsulant. the optical die is underlying the recess, with the micro lens facing the recess.
Inventor(s): Ming Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lin Shen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Heng Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/017
CPC Code(s): G02F1/017
Abstract: an optical device and method of manufacture is presented. in embodiments a method includes forming a first layer of optical material, patterning the first layer into a stair-step pattern, depositing a dielectric material onto the stair-step pattern, and forming a second layer of optical material over the dielectric material and at least partially within the stair-step pattern.
Inventor(s): Tai-Chun Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/025, G02B6/132
CPC Code(s): G02F1/025
Abstract: in some embodiments, the present disclosure provides an optical module. a waveguide includes a rib, and further includes a first protrusion and a second protrusion respectively on opposite sides of the rib. further, the waveguide is formed of a first semiconductor material. a photodetector is in the waveguide and comprises a pn junction in the rib. a p type region of the pn junction extends to the first protrusion, and an n type region of the pn junction extends to the second protrusion. further, the first and second protrusions accommodate heavily doped p and n type contact regions. a semiconductor region is on the pn junction. the semiconductor region comprises a second semiconductor material different the first semiconductor material. for example, the second semiconductor material may have a smaller bandgap than the first semiconductor material to enhance quantum efficiency.
Inventor(s): Ming Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lin Shen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Heng Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/025, G02F1/015
CPC Code(s): G02F1/025
Abstract: an optical device and methods of manufacturing such optical devices are presented. in embodiments the optical device is a tunable beam splitter which is made by forming a first dopant region over a substrate, the first dopant region comprising a first waveguide and a second waveguide, depositing a cladding material over the first waveguide and the second waveguide, and forming a second dopant region overlying the first waveguide and the second waveguide, wherein the forming the second dopant region comprises forming a first region extending over both the first waveguide and the second waveguide, the first region having a constant concentration of a first dopant.
Inventor(s): Chih-Tsung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chung Cheng of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24, G03F1/52, G03F1/54, G03F1/80
CPC Code(s): G03F1/24
Abstract: a lithography mask includes a substrate that contains a low thermal expansion material (ltem). the lithography mask also includes a reflective structure disposed over the substrate. the reflective structure includes a first layer and a second layer disposed over the first layer. at least the second layer is porous. the mask is formed by forming a multilayer reflective structure over the ltem substrate, including forming a plurality of repeating film pairs, where each film pair includes a first layer and a porous second layer. a capping layer is formed over the multilayer reflective structure. an absorber layer is formed over the capping layer.
Inventor(s): Chih-Chiang Tu of Tauyen (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Lang Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jheng-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/26, G03F1/22, G03F1/24, G03F1/52, G03F1/54, G03F1/80, H01L21/033
CPC Code(s): G03F1/26
Abstract: a mask includes a reflective layer, an absorption layer, a buffer layer and an absorption part. the absorption layer is disposed over the reflective layer. the buffer layer is disposed between the reflective layer and the absorption layer. the absorption part is disposed in the reflective layer, the buffer layer and the absorption layer.
Inventor(s): Yun-Yue LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/62, G03F7/00
CPC Code(s): G03F1/62
Abstract: a pellicle for an euv photo mask includes a base membrane layer, a core layer disposed over the base membrane layer and one or more metallic layers disposed over the core layer.
Inventor(s): Chen-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuan Wei LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsien LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng TUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang Yin SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/66, G03F1/84, G03F7/00, G05B19/418, G06N20/00
CPC Code(s): G03F1/66
Abstract: a storage environment monitoring device is capable of measuring and/or monitoring various parameters of an environment inside a storage area, such as airflow, temperature, and humidity, to increase the storage quality of semiconductor components stored in the storage area. the storage environment monitoring device is capable of measuring and/or monitoring the parameters of the environment inside the storage area without having to open an enclosure that is storing the semiconductor components in the storage area. this reduces exposure of the semiconductor components to contamination and other environmental factors. in addition, the storage environment monitoring device may perform automatic measurements inside the storage area based on usage schedules of the semiconductor components that are to be stored in the storage area, which decreases downtime of the storage area and/or the semiconductor components, and increases productivity in a semiconductor processing environment in which the semiconductor components are used.
Inventor(s): An-Ren Zi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Joy Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/30, G03F7/32, G03F7/36
CPC Code(s): G03F7/0042
Abstract: the present disclosure provides a method for lithography patterning in accordance with some embodiments. the method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.
Inventor(s): Chih-Cheng Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Hung Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Ming Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/16
CPC Code(s): G03F7/0042
Abstract: an organometallic precursor for extreme ultraviolet (euv) lithography is provided. an organometallic precursor includes a chemical formula of mxl, where m is a metal, x is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, l is an extreme ultraviolet (euv) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
Inventor(s): An-Ren Zi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Joy Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004
CPC Code(s): G03F7/0048
Abstract: a photoresist layer is formed over a wafer. the photoresist layer includes a metallic photoresist material and one or more additives. an extreme ultraviolet (euv) lithography process is performed using the photoresist layer. the one or more additives include: a solvent having a boiling point greater than about 150 degrees celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.
Inventor(s): Siao-Shan WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/038, C08L25/08, C08L33/10, C08L33/16, G03F7/004, G03F7/027, G03F7/16, G03F7/20, G03F7/40
CPC Code(s): G03F7/0388
Abstract: a method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. the photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. the photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.
Inventor(s): Chien-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/09, C09D5/00, C09D165/00, G03F7/038, G03F7/039, G03F7/11, G03F7/16, G03F7/20, G03F7/32, G03F7/38
CPC Code(s): G03F7/091
Abstract: a method according to the present disclosure includes providing a substrate, depositing an underlayer over the substrate, depositing a photoresist layer over the underlayer, exposing a portion of the photoresist layer and a portion of the underlayer to a radiation source according to a pattern, baking the photoresist layer and underlayer, and developing the exposed portion of the photoresist layer to transfer the pattern to the photoresist layer. the underlayer includes a polymer backbone, a polarity switchable group, a cross-linkable group bonded to the polymer backbone, and photoacid generator. the polarity switchable group includes a first end group bonded to the polymer backbone, a second end group including fluorine, and an acid labile group bonded between the first end group and the second end group. the exposing decomposes the photoacid generator to generate an acidity moiety that detaches the second end group from the polymer backbone during the baking.
Inventor(s): Jing CHANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hai YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hsiang TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/16, G05B13/02, G06T7/00, G06T7/60, H01L21/027, H01L21/66, H04N23/90
CPC Code(s): G03F7/16
Abstract: an apparatus for manufacturing a semiconductor device includes a fluid dispense nozzle configured to dispense a photoresist composition on a semiconductor substrate, and a first camera configured to obtain a first image of the fluid dispense nozzle. the apparatus further includes a second camera configured to obtain a second image of the fluid dispense nozzle, the second image having a higher resolution than the first image, and an image recognition system operably coupled to the first and second cameras. the image recognition system includes a memory storing instructions and at least one processor that executes the instructions to obtain an image of a benchmark fluid dispense nozzle using the second camera, and determine a width of the benchmark fluid dispense nozzle at multiple intervals along the benchmark fluid dispense nozzle and a width of a spray pattern of the photoresist composition being dispensed from the benchmark fluid dispense nozzle.
Inventor(s): Tai-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G21K1/06, H05G2/00
CPC Code(s): G03F7/70033
Abstract: a photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. the photolithography system irradiates the droplets with a laser. the droplets become a plasma and emit extreme ultraviolet radiation. an array of sensors sense the extreme ultraviolet radiation and charged particles emitted by the droplets. a control system analyses sensor signals from the sensors and adjusts plasma generation parameters responsive to the sensor signals.
Inventor(s): Peter Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tung Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kevin Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chia Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Roger Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/38, G03F1/42, G03F1/70
CPC Code(s): G03F7/70475
Abstract: examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. in some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. the stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.
Inventor(s): Yu-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Tsung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Yu WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/706845
Abstract: to improve quality assurance and durability of coated components, a multifaceted inspection coupon is provided that includes opposing flat surfaces, separated by sides which include one or more curves or fillets representing surfaces of the coated components to be inspected. the inspection coupon is coated on all sides in the same manner as the components to be inspected, whereby later analysis of the coupon provides quality assurance of all coated surfaces of the components at once.
Inventor(s): Yu-Huan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chih HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-An PENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70725
Abstract: a semiconductor substrate stage for carrying a substrate is provided. the semiconductor substrate stage includes a carrier layer, a storage layer having an energy storage device and a water storage device, a magnetic shielding layer disposed between the carrier layer and the storage layer, and a receiver disposed in a recess of the carrier layer and partially exposed from the carrier layer.
Inventor(s): Shih-Yu TU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chieh HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H05G2/00
CPC Code(s): G03F7/7085
Abstract: an extreme ultraviolet (euv) photolithography system detects debris travelling from an euv generation chamber to a scanner. the photolithography system includes a detection light source and a sensor. the detection light source outputs a detection light across a path of travel of debris particles from the euv generation chamber. the sensor senses debris particles by detecting interaction of the debris particles with the detection light.
Inventor(s): Yen-Hui LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzung-Chi FU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/82, H05G2/00
CPC Code(s): G03F7/70925
Abstract: an extreme ultraviolet (euv) photolithography system cleans debris from an euv reticle. the system includes a cleaning electrode configured to be positioned adjacent the euv reticle. the system includes a voltage source that helps draw debris from the euv reticle toward the cleaning electrode by applying a voltage of alternating polarity to the cleaning electrode.
Inventor(s): Cheng-Kang HU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hung CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Han CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Kuang WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Shui LIU of Pingjhen City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shou-Wen KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05D1/00, B25J5/00, G01S17/931
CPC Code(s): G05D1/0214
Abstract: in an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.
Inventor(s): Rong Syuan FAN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng TUNG of Jhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang Yin SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05D1/00, B65G1/137, G06Q10/087
CPC Code(s): G05D1/0278
Abstract: a mobile stocker described herein is configured to be easily installed and relocated to various locations in a semiconductor fabrication facility. the mobile stocker is capable of being programmed with, and/or autonomously learning, the layout of a semiconductor fabrication facility, and automatically relocating to a new location based on the layout using a navigation system. accordingly, the mobile stocker is capable of being flexibly relocated in the semiconductor fabrication facility to dynamically support changes in demand and production capacity. moreover, the capability to quickly assign a location identifier to the mobile stocker and to automatically interface with transport systems in the semiconductor fabrication facility reduces downtime of the mobile stocker, which increases productivity in the semiconductor fabrication facility.
Inventor(s): Meng-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F13/40, G11C29/08
CPC Code(s): G06F13/4027
Abstract: a memory device includes a first memory block. the first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. the first interface portion has a plurality of first control structures formed as a first staircase profile. the first memory block further includes a plurality of first interconnect structures landing on a corresponding one of the plurality of first control structures, and a plurality of second interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a first transistor. the memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. the first and second test structures are electrically coupled to each other and are electrically isolated form the first memory block.
Inventor(s): Shih-Wei Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsin Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, H01L23/528
CPC Code(s): G06F30/392
Abstract: in some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (pg), are removed after the layout process through a computer-implemented process analogous to solving the n-coloring problem. through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.
Inventor(s): I-Shuo Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chun Hsia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Ting Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuanhua Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., William Weilun Hong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kei-Wei Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F111/20, G06T7/00
CPC Code(s): G06F30/392
Abstract: a method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. the step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. the method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. the position is the position of the corresponding image in the layout.
Inventor(s): Ming-Chieh TSAI of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu WANG of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/396, G06F1/10, G06F30/392
CPC Code(s): G06F30/396
Abstract: a method and system for generating a clock distribution circuit for each macro circuit in an asic design are disclosed herein. in some embodiments, a method for generating a clock distribution circuit receives the asic design specified in a hardware description language (hdl), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the asic design, and outputs a physical layout of the asic design for manufacturing under a semiconductor fabrication process.
Inventor(s): Meng TAI of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Chia-Chun LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., ShiWen TAN of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Song LIU of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd., Cheng JIN of Nanjing City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/392
CPC Code(s): G06F30/398
Abstract: a method is provided, including following operations: receiving, by a static voltage drop (sir) prediction circuitry, floorplan data of a floorplan layout of a semiconductor device; generating a first sir result by a machine learning model based on the floorplan data; generating a first similarity value based on a comparison of the floorplan data with a plurality of training data; generating a second sir result based on the first sir result and a first compensation value, corresponding to the first similarity value, in a mapping table; and generating a bump assignment data to update the floorplan data based on a comparison between the second sir result with a plurality of predetermined sir values.
Inventor(s): Nuo Xu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Zhengping Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Ting Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsing Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06T7/00, G06T15/08
CPC Code(s): G06T7/0004
Abstract: the present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. the method includes initializing a voxel mesh as a three-dimensional (3d) representation of a physical structure by a central processing unit (cpu), generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a graphics processing unit (gpu), identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread in the gpu, passing parameters describing the one of the particles hitting the voxel mesh from the gpu to the cpu, determining a surface reaction between the one of the particles and the voxel unit by the cpu, and updating the voxel mesh based on the determining of the surface reaction.
Inventor(s): Zhi-Hao Chang of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-jer Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yangsyu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4074, G11C11/4072, G11C11/4093
CPC Code(s): G11C11/4074
Abstract: a power control device includes a first switch and a second switch. a first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. a second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. the control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.
Inventor(s): Mahmut Sinangil of Campbell CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/408, G11C11/4093, G11C11/4094, H03M1/80
CPC Code(s): G11C11/4085
Abstract: an example computing device includes an array of memory cells, such as 8-transistor sram cells, where the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. the computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. the output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, where the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. a method of making a computing device as described is also disclosed.
Inventor(s): Yumito Aoyagi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuichiro Ishii of Kanazawa-Ku (JP) for taiwan semiconductor manufacturing company, ltd., Makoto Yabuuchi of Tokyo (JP) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418, G11C11/419
CPC Code(s): G11C11/418
Abstract: a memory macro includes a tracking wordline driver that drivers a wordline with a suppressed voltage. the suppressed voltage is made lower than the voltage used to drive wordlines in the memory array by an amount that a tracking wordline is driven with a suppressed voltage, which is a voltage that is held below the drain supply voltage. suppressing the voltage on the tracking wordline causes tracking memory cell with average cell characteristic to emulate the slowest memory cells in a memory array. the tracking wordline with the suppressed voltage may be subjected to a mimicked wordline load. the tracking wordline with the suppressed voltage and the mimicked wordline load may also be used to enable a mimicked write drive used in write tracking. the tracking wordline with the suppressed voltage may also be used as input to a write delay circuit that times write operations.
Inventor(s): Zheng-Jun LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-I SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Cheng CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/412, G11C13/00, G11C14/00, H03K19/20, H03K19/21
CPC Code(s): G11C11/419
Abstract: a memory device including a static random-access memory that includes two cross-coupled inverters and an access transistor having a gate connected to a word line. the memory device further includes one or more logic gates electrically coupled to the static random-access memory, and a non-volatile memory electrically coupled to the static random-access memory and configured to store data and be read using the static random-access memory, wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/04, G11C7/18, H10B41/10, H10B41/20, H10B43/10, H10B43/20
CPC Code(s): G11C16/0483
Abstract: a method for manufacturing a semiconductor device includes forming a first memory cell, which includes forming a first conductor structure extending along a lateral direction; forming a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; forming a first semiconductor film wrapping around the first portion of the first memory film; forming a second conductor structure that extends along a vertical direction; coupling the second conductor structure to a first end portion of the first semiconductor film along the lateral direction; forming a third conductor structure extends along the vertical direction; and coupling the third conductor structure to a second end portion of the first semiconductor film along the lateral direction. the first conductor structure has a void.
Inventor(s): Po-Hao Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Der Chih of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/44, G11C11/16
CPC Code(s): G11C29/4401
Abstract: a method for testing and repairing a memory device is provided. the memory device includes a memory array having data cells and reference cells arranged along cell rows and cell columns. the data cells are configured to store data, and the reference cells are configured to generate a reference current for reading the data stored in the data cells. the method includes: performing a row repair, to test the reference cells in each cell row, and to replace the cell row containing at least one defective reference cell by a redundant cell row comprising additional data cells and additional reference cells; and performing a local reference current trimming, to modify a ratio of an amount of the reference cells programmed with a low resistance state over an amount of the reference cells programmed with a high resistance state for at least one of the cell rows.
Inventor(s): Cheng Hung TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Kang YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G21K1/06, G02B5/08, G03F7/00, H05G2/00
CPC Code(s): G21K1/06
Abstract: an extreme ultra violet (euv) light source apparatus includes an excitation laser inlet port configured to receive an excitation laser, and a first mirror configured to reflect the excitation laser that passes through a zone of excitation. a metal droplet is irradiated by the excitation laser.
Inventor(s): Luc Thomas of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Guenole Jan of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Ru-Ying Tong of Los Gatos CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01F10/12, B24B37/20, G03F7/16, G11C11/16, H01F41/30, H10N35/01, H10N50/01, H10N50/10, H10N50/85
CPC Code(s): H01F10/123
Abstract: an improved magnetic tunnel junction with two oxide interfaces on each side of a ferromagnetic layer (fml) leads to higher pma in the fml. the novel stack structure allows improved control during oxidation of the top oxide layer. this is achieved by the use of a fml with a multiplicity of ferromagnetic sub-layers deposited in alternating sequence with one or more non-magnetic layers. the use of non-magnetic layers each with a thickness of 0.5 to 10 angstroms and with a high resputtering rate provides a smoother fml top surface, inhibits crystallization of the fml sub-layers, and reacts with oxygen to prevent detrimental oxidation of the adjoining ferromagnetic sub-layers. the fml can function as a free or reference layer in an mtj. in an alternative embodiment, the non-magnetic material such as mg, al, si, ca, sr, ba, and b is embedded by co-deposition or doped in the fml layer.
Inventor(s): Po-Hsiang Wang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Chang Ching of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo Liang Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Han Chu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/3244
Abstract: the present disclosure relates to an integrated chip processing tool. the integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. the gas distribution ring includes a lower ring extending around the process chamber. the lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. the gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. a plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. a plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.
Inventor(s): Jung-Hao Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chin CHANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Li-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, H01L21/263, H01L21/687
CPC Code(s): H01J37/32651
Abstract: the present disclosure relates to a semiconductor device manufacturing system. the semiconductor device manufacturing system can include a chamber and an ion source in the chamber. the ion source can include an outlet. the ion source can be configured to generate a particle beam. the semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. a first portion of the grid structure can be electrically insulated from a second portion of the grid structure.
Inventor(s): Po-Chuan Wang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Xuan Chen of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yang Hung of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Liang Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Just Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/311, H01L21/768
CPC Code(s): H01L21/02063
Abstract: a method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
Inventor(s): Wei-Che Hsieh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Hao Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chunyao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/033, H01L21/308, H01L21/762, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L21/0217
Abstract: a method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. the process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.
Inventor(s): Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C23C16/455, H01L21/383, H01L21/443, H01L21/8234, H01L27/088, H01L29/66
CPC Code(s): H01L21/0228
Abstract: a method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ald) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chi Ko of Nantou (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/324, H01L21/762, H01L29/66, H01L29/78
CPC Code(s): H01L21/02362
Abstract: a method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (nh) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. the dielectric barrier layer comprises silicon and nitrogen.
Inventor(s): Tz-Shian CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027
CPC Code(s): H01L21/0272
Abstract: a method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. in some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. in some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.
Inventor(s): Tz-Shian CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027
CPC Code(s): H01L21/0272
Abstract: a method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. in some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. in some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.
Inventor(s): Wei-Chao CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Jin LIOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wei CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Sen KUO of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Jia SHIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/04, H01L21/266
CPC Code(s): H01L21/0332
Abstract: implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. the pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. in this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
Inventor(s): Tsong-Hua Ou of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ken-Hsien Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chun Huang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng Gau of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/027, H01L21/311, H01L21/321, H01L21/3213
CPC Code(s): H01L21/0338
Abstract: the present disclosure provides a method of patterning a target material layer over a semiconductor substrate. the method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. a portion of the first feature extends over the spacer feature. the method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. other methods and associated patterned semiconductor wafers are also provided herein.
Inventor(s): Chun-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En Lin of Xionglin Township (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, H01L21/308
CPC Code(s): H01L21/0338
Abstract: a method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. the method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.
Inventor(s): Chih-Chuan SU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh HSIAO of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/225, H01L21/768, H01L23/00, H01L23/532, H01L25/065
CPC Code(s): H01L21/2251
Abstract: a semiconductor device structure and a formation method are provided. the method includes forming an opening in a semiconductor body, and the semiconductor body is p-type doped. the method also includes introducing n-type dopants into the semiconductor body to form a modified portion near the opening, and the modified portion is p-type doped. the method further includes forming a dielectric layer along the sidewalls and the bottom of the opening. in addition, the method includes forming a conductive structure over the dielectric layer to fill the opening.
Inventor(s): Yu-Jiun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Hao Tsao of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Han Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Jhih Syu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng Yu of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Yun Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/285, H01L21/311, H01L21/3115, H01L21/8234, H01L21/8238, H01L29/08, H01L29/423, H01L29/45, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L21/28132
Abstract: in an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.
Inventor(s): Kuo-Feng Yu of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun Hsiung Tsai of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hoong Shing Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Hsu of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/033, H01L21/311, H01L21/8234, H01L21/8238, H01L27/092, H01L29/66
CPC Code(s): H01L21/28176
Abstract: a method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. the hard mask is free from both of titanium and tantalum. the method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.
Inventor(s): Kuei-Lun Lin of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Hsu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Xiong-Fei Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Hsu of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/285, H01L21/3205, H01L21/3213, H01L21/8234, H01L21/8238, H01L27/088, H01L27/092, H01L29/66
CPC Code(s): H01L21/28185
Abstract: in an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.
Inventor(s): Mao-Lin HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/28247
Abstract: a method for processing an integrated circuit includes forming n-type and p-type gate all around transistors and core gate all around transistors. the method deposits a metal gate layer for the p-type transistors. the method forms a passivation layer in-situ with the metal gate layer of the p-type transistor.
Inventor(s): Yu-Hsing Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming Chyi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang Liu of Alian Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3065, H01L21/308
CPC Code(s): H01L21/30655
Abstract: some embodiments pertain to a semiconductor device. the semiconductor device includes a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. the trench includes a bottom surface and a plurality of scallops along sidewalls of the trench. an oxide layer lines the bottom surface and the sidewalls of the trench. the oxide layer has varying thicknesses along the sidewalls of the trench at different depths. the varying thicknesses step down at discrete increments as a depth into the trench increases.
Inventor(s): Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3105, H01L21/02, H01L21/027, H01L21/3065, H01L21/463
CPC Code(s): H01L21/31055
Abstract: a manufacturing method of a semiconductor structure includes: forming a liner structure on an inner sidewall of a dielectric layer overlying a semiconductor substrate; forming a via hole in an area of the semiconductor substrate which is exposed by the liner structure, wherein an overhang portion of the semiconductor substrate having a tapering arc-shaped profile and overhanging the via hole is formed; and filling the via hole with a conductive material.
Inventor(s): Pang-Sheng Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Feng Yin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsun Wang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Yi Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Yu Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Yuan Kao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yang Hung of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Huei Suen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jyu-Horng Shieh of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Liang Pan of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jack Kuo-Ping Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Jyun Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/321, H01L21/28, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L21/321
Abstract: a semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. the conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. the gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.
Inventor(s): Sheng-Chun YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chih HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lung CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Min-Cheng CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/324, H01L21/67
CPC Code(s): H01L21/324
Abstract: a system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. a gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.
Inventor(s): Tzung-Yi Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Kang Ho of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/324, H01L21/768, H01L29/161, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H01L21/324
Abstract: a semiconductor device is provided. the semiconductor device has a fin structure that protrudes vertically upwards. a lateral dimension of the fin structure is reduced. a semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. an annealing process is performed to the semiconductor device after the forming of the semiconductor layer. a dielectric layer is formed over the fin structure after the performing of the annealing process.
Inventor(s): Po-Lung HUNG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Tsang HSIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsi TANG of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ching CHENG of Xizhou Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01J37/32
CPC Code(s): H01L21/67069
Abstract: in a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. the emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. the flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.
Inventor(s): Yu-Chen CHEN of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung WU of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Ann CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ren-Hau WU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, G01F1/00, G01M3/32, G01M9/06, H01L21/673, H01L21/677
CPC Code(s): H01L21/67253
Abstract: an airflow detection device is capable of detecting airflow issues associated with a transport carrier, such as a blockage of a diffuser in a transport carrier or leakage of a transition bracket, among other examples. the airflow detection device includes an air tunnel through which a gas in a transport carrier may flow. the airflow detection device includes an airflow sensor configured to generate airflow data based on a flow of the gas through the air tunnel. in some implementations, the airflow detection device is included in an airflow detection system to perform automated measurements and to determine, identify, and/or detect airflow issues associated with a transport carrier. in this way, the airflow detection system may perform one or more automated actions (or may cause one or more other devices to perform one or more automated actions) based on a detection of a diffuser blockage or a transition bracket leak.
Inventor(s): Tsung-Sheng KUO of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Wei HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Ann CHU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Shui LIU of Pingjhen City, Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/02, H01L21/66
CPC Code(s): H01L21/67288
Abstract: in certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.
Inventor(s): Tung-Huang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hao KUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/673, H01L21/324, H01L21/67, H01L21/687
CPC Code(s): H01L21/67323
Abstract: a substrate boat for use in heat treatment of semiconductor wafers includes support rods and fingers for supporting a substrate in a horizontal orientation in process tools, e.g., furnaces. the substrate is supported in the substrate boat by groups of fingers lying in a common horizontal plane. the fingers contact the substrate at support locations on the back side of the substrate. the fingers have a plurality of different shapes and a substrate surface no contact region.
Inventor(s): Yan-Chun LIU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yii-Chi LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu MA of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Jang LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Lun LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/68, C23C16/02, C23C16/52, H01L21/687
CPC Code(s): H01L21/681
Abstract: in some implementations, a control device may determine a spacing measurement in a first dimension between a wafer on a susceptor and a pre-heat ring of a semiconductor processing tool and/or a gapping measurement in a second dimension between the wafer and the pre-heat ring, using one or more images captured in situ during a process by at least one optical sensor. accordingly, the control device may generate a command based on a setting associated with the process being performed by the semiconductor processing tool and the spacing measurement and/or the gapping measurement. the control device may provide the command to at least one motor to move the susceptor.
Inventor(s): Ting-Jung Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lee-Chuan Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, C23C14/50, C23C14/54, C23C14/58, C23C16/458, C23C16/46, H01J37/32, H01L21/67, H01L21/768
CPC Code(s): H01L21/6833
Abstract: in some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. the wafer chuck structure is configured to hold a wafer during a fabrication process. the wafer chuck includes a lower portion and an upper portion arranged over the lower portion. the lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. the upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. multiple of the openings directly overlie each trench. further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.
Inventor(s): Chung-Pin CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Lin CHUANG of Chia-Yi City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Wen HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Cheng CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jun Xiu LIU of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683
CPC Code(s): H01L21/6833
Abstract: some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. the voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. the voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. while positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.
Inventor(s): Jen-Chun Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Yueh Wu of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Ling Hwang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683, H01L21/67, H01L21/687
CPC Code(s): H01L21/6838
Abstract: a method for handling a semiconductor substrate includes: placing a semiconductor substrate over a semiconductor apparatus, where a central portion of the semiconductor substrate overlies a carrying surface of a chuck table of the semiconductor apparatus, an edge portion of the semiconductor substrate overlies a top surface of a first flexible member of the semiconductor apparatus, the first flexible member is disposed within a recess of the chuck table and extends along a perimeter of the carrying surface, and a gap forms among the semiconductor substrate, the carrying surface of the chuck table, and the top surface of the first flexible member; and introducing a vacuum in vacuum holes in the chuck table to form a vacuum seal among the semiconductor substrate, the chuck table, and the first flexible member.
Inventor(s): Wen-Yen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Chen Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Cyuan Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/02, H01L21/764, H01L21/768
CPC Code(s): H01L21/76224
Abstract: a method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. in the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. after the laser reflow process, the trench-filling material is solidified. the method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
Inventor(s): Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lu Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/311, H01L27/088
CPC Code(s): H01L21/76224
Abstract: a method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. a masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. after depositing the masking layer, a first portion of an ild layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. after etching the first portion of the ild layer, the masking layer is etched to form an l-shaped masking layer. after forming the l-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
Inventor(s): Ya-Ching Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Wen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76808
Abstract: a method according to the present disclosure includes receiving a workpiece that includes a first source/drain feature, a first dielectric layer over the first source/drain feature, and a source/drain contact disposed in the first dielectric layer and over the first source/drain feature. the method further includes depositing a second dielectric layer over the source/drain contact and the first dielectric layer, forming a source/drain contact via opening through the second dielectric layer to expose the source/drain contact, depositing a sacrificial plug in the source/drain contact via opening, depositing a third dielectric layer over the second dielectric layer and the sacrificial plug, forming a trench in the third dielectric layer to expose the sacrificial plug, removing the sacrificial plug to expose the source/drain contact via opening, and after the removing of the sacrificial plug, forming an integrated conductive feature into the trench and the exposed source/drain contact via opening.
Inventor(s): Cheng-Chin LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/7682
Abstract: a method for forming an interconnect structure is described. in some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.
Inventor(s): Yi-Nien Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Wei Huang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Min Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/7682
Abstract: a method includes etching a dielectric layer to form an opening. a first conductive feature underlying the dielectric layer is exposed to the opening. a sacrificial spacer layer is deposited to extend into the opening. the sacrificial spacer layer is patterned. a bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. a second conductive feature is formed in the opening. the second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. at least a portion of the ring is removed to form an air spacer.
Inventor(s): Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768
CPC Code(s): H01L21/76831
Abstract: a method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. the thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.
Inventor(s): Bo-Jiun Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768
CPC Code(s): H01L21/76834
Abstract: provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.
Inventor(s): Yu-Lien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Feng FU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Just LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Ming HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L23/522, H01L23/532, H01L29/66, H01L29/78
CPC Code(s): H01L21/76837
Abstract: a semiconductor structure includes a gate, a self-aligned contact (sac) layer that is disposed on the gate and that has a seam at a top surface of the sac layer, a gate spacer that is formed on a sidewall of the gate, and a metal contact that is disposed adjacent to the gate spacer and that is spaced apart from the gate by the gate spacer. the sac layer includes a filler that seals the seam in the sac layer, and a top surface of the filler is coplanar with a top surface of the gate spacer and a top surface of the metal contact.
Inventor(s): Sheng-Tsung WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/76846
Abstract: a device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. the device includes a gate via in contact with the first gate structure. the gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
Inventor(s): Chien CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Min-Hsiu HUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shiuan WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tai Min CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kan-Ju LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Shiun CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi HUANG of Hsin-chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532, H01L23/535
CPC Code(s): H01L21/76846
Abstract: a barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. the barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. the barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. this enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
Inventor(s): Bo-Yu Lai of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Szu Lee of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hua Wu of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin Liang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Chu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532, H01L29/40, H01L29/417, H01L29/45, H01L29/66
CPC Code(s): H01L21/76867
Abstract: a method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.
Inventor(s): Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzy-Kuang Lee of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Hao Chun Liu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsien Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/48, H01L21/60, H01L23/00, H01L23/532
CPC Code(s): H01L21/76877
Abstract: a method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. the passivation layer has sidewalls facing the second opening. a planarization layer is dispensed on the passivation layer. the planarization layer is patterned to form a third opening. after the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. an under-bump metallurgy (ubm) is formed to extend into the third opening.
Inventor(s): Shu-Cheng Chin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Hsiang Chan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien Chi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Su of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3105, H01L21/3213, H01L23/522, H01L23/532
CPC Code(s): H01L21/76885
Abstract: a method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. the second conductive feature is over and electrically connected to the graphite conductive feature.
Inventor(s): Shih-Che Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsun Wang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hsien Yao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/528, H01L23/535
CPC Code(s): H01L21/76895
Abstract: a method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. a contact etch stop layer (cesl) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the cesl having a snake-like pattern disposed over the substrate topography. a contact via opening is formed in a dielectric layer disposed over the cesl, where the contact via opening exposes a portion of the cesl within the trench. the portion of the cesl exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. a metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.
Inventor(s): Pin-Wen Chen of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Han Lai of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Hui Fu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing Tsai of Chu-Pei (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jung Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shih Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Yi Cheng of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., I-Li Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/285, H01L21/3213, H01L23/535
CPC Code(s): H01L21/76895
Abstract: the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. in some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
Inventor(s): Hsin-Ping Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3213, H01L23/522, H01L23/528
CPC Code(s): H01L21/76897
Abstract: the present disclosure provides a method of forming a semiconductor structure. the method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. the method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.
Inventor(s): Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76897
Abstract: a method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.
Inventor(s): Cai-Ling Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Wen Hsueh of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Ping Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Neng-Jye Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3213, H01L23/522, H01L23/532
CPC Code(s): H01L21/76897
Abstract: the present disclosure provides an exemplary semiconductor structure that includes a substrate having a conductive feature disposed in a top portion of the substrate, a metal line above the substrate and in electrical coupling with the conductive feature, a dielectric feature disposed on a sidewall of the metal line, an etch stop layer disposed on the dielectric feature and the meta line, and a via extending through the etch stop layer and in physical contact with top surfaces of the dielectric feature and the metal line. the metal line has a first metal, and the via has a second metal different from the first metal. the top surface of the dielectric feature is higher than the top surface of the metal line.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/3065, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L21/76898
Abstract: an embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.
Inventor(s): Chao-Ching Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ang Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/786, H10K10/46, H10K71/12, H10K85/20
CPC Code(s): H01L21/823412
Abstract: a method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. a transistor is then formed based on the protruding fin.
Inventor(s): Ke-Ming CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chen CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tsang TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, G11C5/06, H01L21/02, H01L21/768, H01L21/8238, H01L29/40, H01L29/417, H10B10/00
CPC Code(s): H01L21/823418
Abstract: a method of forming a semiconductor structure is provided. the method includes forming a gate structure over an active region of a substrate, forming an epitaxial layer comprising first dopants of a first conductivity type over portions of the active region on opposite sides of the gate structure, the epitaxial layer, applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer, forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer, forming a contact region second dopants of a second conductivity type opposite the first conductivity type in the portion of the epitaxial layer not covered by the patterned photoresist layer, and forming a contact overlying the contact region.
Inventor(s): Xusheng Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Keung Leung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huiling Shang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L21/823418
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (s/d) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk s/d feature is separated from the substrate by a first air gap, and the bulk s/d feature is separated from the inner spacers by second air gaps.
Inventor(s): Chia-Yun CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Ming CHANG of ShinChu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66
CPC Code(s): H01L21/823431
Abstract: a method for forming a semiconductor device structure includes forming a fin structure over a substrate. the method also includes forming a dummy gate structure across the fin structure. the method also includes depositing a spacer layer over the fin structure and the dummy gate structure. the method also includes implanting dopants into the spacer layer to form a first doped region vertically overlapping the dummy gate structure and a second doped region over the fin structure without vertically overlapping the dummy gate structure. a middle region of the spacer layer connects the first doped region and the second doped region. the method also includes removing the first doped region and the second doped region of the spacer layer. the method also includes forming a source/drain structure attached to the fin structure after removing the first doped region and the second doped region of the spacer layer.
Inventor(s): Chia-Hao Pao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jo-Chun Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsiang Chan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kuan Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lien-Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L21/823431
Abstract: a method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/306, H01L21/308, H01L21/311, H01L21/8238, H01L27/088, H01L27/092, H01L29/66
CPC Code(s): H01L21/823431
Abstract: fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different ic regions. an exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. the first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin finfet and a second spacing in a second region corresponding with a multi-fin finfet. the first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.
Inventor(s): Yu-Chang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Shun Chang of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Feng Nieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/223, H01L21/265, H01L21/8238, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L21/823431
Abstract: a method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. the first impurities have a lower formation enthalpy than the second impurities. the method further includes after implanting the second impurities, annealing the source/drain region.
Inventor(s): Hsin-Han Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chiang Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/28, H01L27/088, H01L29/49
CPC Code(s): H01L21/82345
Abstract: a method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. the work-function layer, the silicon layer, and the glue layer are in-situ deposited. the method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
Inventor(s): Pei Ying LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei HSU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Da LIN of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H01L21/823462
Abstract: a semiconductor structure is provided. the semiconductor structure includes a first n-type transistor having a first threshold voltage and including a first gate dielectric layer, and a second n-type transistor having a second threshold voltage and including a second gate dielectric layer. the first threshold voltage is lower than the second threshold. each of the first gate dielectric layer and the second gate dielectric layer contains fluorine and hafnium. the first gate dielectric layer has a first average fluorine concentration and a first average hafnium concentration. the second gate dielectric layer has a second average fluorine concentration and a second average hafnium concentration. a first ratio of the first average fluorine concentration to the first average hafnium concentration is greater than and a second ratio of the second average fluorine concentration to the second average hafnium concentration.
Inventor(s): Yi Chen Ho of Taiching (TW) for taiwan semiconductor manufacturing company, ltd., Yiting Chang of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zheng-Yang Pan of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/762, H01L27/088
CPC Code(s): H01L21/823481
Abstract: in an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.
Inventor(s): Min-Yann Hsieh of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hua Feng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/3105, H01L21/762, H01L27/088
CPC Code(s): H01L21/823481
Abstract: a semiconductor device includes. a first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. a first dielectric fin is located between the first epi-layer and the second epi-layer. the first dielectric fin has a first dielectric constant. a third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. a second dielectric fin is located between the third epi-layer and the fourth epi-layer. the second dielectric fin has a second dielectric constant that is less than the first dielectric constant.
Inventor(s): Hui-Lin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of Chubei (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng Li of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/033, H01L21/285, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L21/823814
Abstract: a method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. the method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.
Inventor(s): I-Hsieh Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/823814
Abstract: a semiconductor structure and a method of forming the same are provided. in an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. the method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (fsw) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the fsw spacers, and replacing the dummy gate structure with a gate stack.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/823814
Abstract: a cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. the asymmetric cladding sidewall layers enable asymmetric metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. this may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.
Inventor(s): Jhon-Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/311, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L21/823821
Abstract: a method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (sti) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.
Inventor(s): Chun-Han Chen of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/285, H01L21/311, H01L27/092, H01L29/08, H01L29/165, H01L29/267, H01L29/417, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L21/823871
Abstract: in an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (cesl) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor cesl including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/768, H01L23/522, H01L23/528, H01L27/092, H01L29/08
CPC Code(s): H01L21/823871
Abstract: interconnect structures and corresponding formation techniques for fin-like field effect transistors (finfets) are disclosed herein. an exemplary interconnect structure for a finfet includes a gate node via electrically coupled to a gate of the finfet, a source node via electrically coupled to a source of the finfet, and a drain node via electrically coupled to a drain of the finfet. a source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. the source node via dimension ratio is greater than the drain node via dimension ratio. in some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.
Inventor(s): Szu-Ying Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Hong Syue of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/762, H01L27/092
CPC Code(s): H01L21/823878
Abstract: in an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.
Inventor(s): Hong-Shyang Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming Wu of Hsunchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8258, H01L21/762, H01L21/768, H01L21/84, H01L23/535, H01L27/12
CPC Code(s): H01L21/8258
Abstract: in an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.
Inventor(s): Sheng He HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Pin CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shiue-Ming GUO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Chia KAO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Cheng CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Ching KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jun Xiu LIU of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G01N21/95, G02B27/14
CPC Code(s): H01L22/12
Abstract: in a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. the two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. in response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. the received two or more reflected beams of light are detected to generate two or more detected signals. the two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.
Inventor(s): Po-Chien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hung LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei WEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G03F1/74, G06T7/00
CPC Code(s): H01L22/12
Abstract: one or more embodiments of the present disclosure describe an artificial intelligence assisted substrate defect repair apparatus and method. the ai assisted defect repair apparatus employs an object detection algorithm. based on the plurality of images taken by detectors located at different respective positions, the detectors capture various views of an object including a defect. the composition information as well as the morphology information (e.g., shape, size, location, height, depth, width, length, or the like) of the defect and the object are obtained based on the plurality of images. the object detection algorithm analyzes the images and determines the type of defect and the recommends a material (e.g., etching gas) and the associated information (e.g., supply time of the etching gas, flow rate of the etching gas, etc.) for fixing the defect.
Inventor(s): Hau-Yi Hsiao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun Liang Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G01N21/95, H01L21/56
CPC Code(s): H01L22/26
Abstract: the present disclosure relates to a method and an associated process tool. the method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. the electromagnetic radiation is scanned along a vertical axis. an intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. a position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.
Inventor(s): Jui Fu Hsieh of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chi Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng Tai of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L21/311
CPC Code(s): H01L22/26
Abstract: a method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. the wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. the method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. the end point is an expected time point. the plurality of dielectric regions are etched to the target etching depth. the etching of the plurality of dielectric regions is stopped at the end point.
Inventor(s): Kuang-Wei CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Tsun LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tsung LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong NI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, C23C16/455, C23C16/52, H01L21/02
CPC Code(s): H01L22/26
Abstract: a diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. a sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. in this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. this may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.
Inventor(s): Wen-Yi LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Chun LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/10, H01L21/48, H01L23/00, H01L23/053, H01L23/367, H01L23/552
CPC Code(s): H01L23/10
Abstract: a package structure is provided. the package structure includes a substrate and a ground structure laterally surrounded by the substrate. the package structure also includes a chip-containing structure over the substrate and a protective lid attached to the substrate through a first adhesive element and a second adhesive element. the ground structure is electrically connected to the protective lid through the first adhesive element. the second adhesive element is closer to a corner edge of the substrate than the first adhesive element, and a portion of the second adhesive element is between the first adhesive element and the chip-containing structure.
Inventor(s): Hung-Pin Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/48, H01L23/522, H01L25/10
CPC Code(s): H01L23/3185
Abstract: a semiconductor device and a forming method thereof are provided. the semiconductor device includes an integrated circuit (ic) die and an encapsulant. the ic die includes a semiconductor substrate and an interconnect structure connected to the semiconductor substrate, the semiconductor substrate includes a first ledge, and the interconnect structure includes a second ledge. the encapsulant extends along the first ledge of the first semiconductor substrate and the second ledge of the first interconnect structure.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Fu Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shiang-Hung Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hao Yeh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/762, H01L21/84, H01L23/528, H01L27/12
CPC Code(s): H01L23/367
Abstract: various embodiments of the present disclosure are directed towards an integrated chip (ic). the ic includes a substrate. a semiconductor device is disposed on the substrate. an interlayer dielectric (ild) structure is disposed over the substrate and the semiconductor device. a first intermetal dielectric (imd) structure is disposed over the substrate and the ild structure. an opening is disposed in the first imd structure. the opening overlies at least a portion of the semiconductor device.
Inventor(s): Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng HSU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yi LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/31, H01L23/373, H01L23/433, H01L25/065, H01L25/10
CPC Code(s): H01L23/367
Abstract: a semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. the first thermal interface material and the second thermal interface material have an identical width.
Inventor(s): Chin-Fu Kao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/54, H01L23/00, H01L23/18, H01L23/498, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a manufacturing method of a semiconductor package includes the following steps. a package structure is provided over a substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. a thermal spreader layer is provided over the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region aligned with the gap. a lid structure is provided over the substrate and in contact with the thermal spreader layer.
Inventor(s): Cheng-Chin LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Hsiaokang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/768, H01L23/00, H01L23/498
CPC Code(s): H01L23/373
Abstract: a semiconductor device package, along with methods of forming such, are described. the semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. the semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure. the second thermal feature is in contact with the first thermal feature.
Inventor(s): Yu Chen Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen Yeh of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Kuei Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/31, H01L23/367, H01L23/498, H01L25/065
CPC Code(s): H01L23/3735
Abstract: a semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (tim) films on a first surface of the package distal from the substrate, where each of the tim films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of tim films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of tim films.
Inventor(s): Chieh-En Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L23/00, H01L23/522
CPC Code(s): H01L23/481
Abstract: the problem of connecting a tsv to a beol metal interconnect structure without damaging the beol metal interconnect structure is solved by landing the tsv on a metal coupling structure formed during feol processing. the metal coupling structure is produced in accordance with design rules that apply to feol processing. the metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. the metal coupling structure may include pluralities of the substructures arrayed across the tsv landing area. the substructures that make up the metal coupling structure are connected to the beol metal interconnect through vias.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/48, H01L21/56, H01L23/31
CPC Code(s): H01L23/481
Abstract: a package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. the first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. the bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. the second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. the second insulating encapsulation laterally encapsulates the second semiconductor die.
Inventor(s): Ming-Tsu Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/495, H01L21/18, H01L21/32, H01L21/3213
CPC Code(s): H01L23/49513
Abstract: a method includes forming feature for a first package component, and the forming the feature includes a planarization process to level a top surface of the feature. a silicon-containing dielectric layer is deposited over and contacting the feature, and as a surface feature of the first package component. a second package component is bonded to the silicon-containing dielectric layer through fusion bonding. the silicon-containing dielectric layer has a same thickness in both steps of the depositing and the fusion bonding.
Inventor(s): Su-Jen Sung of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Yao Tu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L23/367
CPC Code(s): H01L23/49822
Abstract: a method includes forming a first bond layer on a first wafer, and forming a first thermal conductive channel extending into the first bond layer. the first thermal conductive channel has a first thermal conductivity value higher than a second thermal conductivity value of the first bond layer. the method further includes forming a second bond layer on a second wafer, and forming a second thermal conductive channel extending into the second bond layer. the second thermal conductive channel has a third thermal conductivity value higher than a fourth thermal conductivity value of the second bond layer. the first wafer is bonded to the second wafer, and the first thermal conductive channel at least physically contacts the second thermal conductive channel. an interconnect structure is formed over the first wafer. the interconnect structure is electrically connected to integrated circuit devices in the first wafer.
Inventor(s): Tuan-Yu Hung of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Feng Yang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Chiang Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/48, H01L23/66, H01Q1/22, H01Q9/04, H01Q9/28
CPC Code(s): H01L23/49827
Abstract: a semiconductor package and a manufacturing method are provided. the manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.
Inventor(s): Lung Yuan Pan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/768, H01L23/00
CPC Code(s): H01L23/49827
Abstract: various embodiments of the present disclosure are directed towards an apparatus comprising a semiconductor substrate. a conductive pillar is disposed in the semiconductor substrate. an isolation region is disposed in the semiconductor substrate and extends laterally around the conductive pillar. the isolation region is configured to electrically isolate the conductive pillar from a surrounding portion of the semiconductor substrate. an opening is disposed in the isolation region. a dielectric anchor is disposed in the isolation region. the dielectric anchor extends vertically through the first semiconductor substrate along a side of the opening. the dielectric anchor anchors the conductive pillar to the semiconductor substrate.
Inventor(s): Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/50, H01L21/8234, H01L23/522, H01L23/528, H01L27/088
CPC Code(s): H01L23/50
Abstract: the present disclosure relates to an integrated chip including a semiconductor device. the semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. the stack of channel structures and the gate structure are between the first and second source/drain structures. the gate structure surrounds the stack of channel structures. a first conductive wire overlies and is spaced from the semiconductor device. the first conductive wire includes a first stack of conductive layers. a first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. the first conductive contact is on a back-side of the first source/drain structure.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Hua Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522
CPC Code(s): H01L23/5223
Abstract: various embodiments of the present disclosure are directed towards a metal-insulator-metal (mim) device. the mim device includes a first conductive layer disposed over a substrate, a first capacitor dielectric disposed over the first conductive layer, and a second conductive layer disposed over the first capacitor dielectric. the first conductive layer and the first capacitor dielectric laterally extend past an outermost sidewall of the second conductive layer. a second capacitor dielectric is disposed over the second conductive layer and the first capacitor dielectric, and a third conductive layer is disposed over the second capacitor dielectric. the third conductive layer laterally extends past the outermost sidewall of the second conductive layer. a conductive structure is coupled to both the first conductive layer and the third conductive layer. the conductive structure extends through the first capacitor dielectric and the second capacitor dielectric laterally outside of the second conductive layer.
Inventor(s): Yuan-Yang Hsiao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Taiwan (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Ching-Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chun Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H10B12/00
CPC Code(s): H01L23/5223
Abstract: a metal-insulator-metal (mim) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. an exemplary device includes a substrate that includes an active semiconductor device. a stack of dielectric layers is disposed over the substrate. a lower contact is disposed over the stack of dielectric layers. a passivation layer is disposed over the lower contact. a mim structure is disposed over the passivation layer, the mim structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. a first insulator layer is disposed between the first conductor layer and the second conductor layer. a second insulator layer is disposed between the second conductor layer and the third conductor layer. one or more corners of the third conductor layer are rounded.
Inventor(s): Yao-Jen TSAI of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Fu CHANG of Pingtung (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Yuan KO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng Chiang HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L27/06
CPC Code(s): H01L23/5223
Abstract: an interconnect structure and methods of forming the same are described. in some embodiments, the structure includes a first intermetal dielectric (imd) layer disposed over a plurality of conductive features and a first passive component disposed on the first imd layer in a first region of the substrate. the structure further includes a second passive component disposed on the first imd layer in a second region of the substrate. the second passive component includes a first conductive layer, and the first conductive layer has a first thickness. the structure further includes a second imd layer disposed on the first passive component in the first region and on the second passive component and a portion of the first imd layer in the second region. the second imd layer has a second thickness ranging from about five times to about 20 times the first thickness.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Yang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522
CPC Code(s): H01L23/5223
Abstract: a device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. the second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. the device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.
Inventor(s): Chun-huan WEI of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Pin Yu HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Yuan CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Po-June CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Yu CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5223
Abstract: disclosed is a method of manufacturing a three dimensional (3d) metal-insulator-metal (mim) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing beol fabrication process. in one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.
Inventor(s): Tzu-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi Tu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H10B51/30
CPC Code(s): H01L23/5226
Abstract: some embodiments relate to a method of forming an integrated chip, including forming a first wire level over a substrate; depositing an etch stop layer over the first wire level; etching the etch stop layer to form an opening over the first wire level; depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening; depositing a first conductive layer over the barrier layer and in the opening; performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer; depositing a data storage layer and a second conductive layer over the first conductive layer; and patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.
Inventor(s): Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jung Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei Chou of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L23/5226
Abstract: an embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. the redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. the third redistribution layer has a third thickness greater than the first thickness and the second thickness. the package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
Inventor(s): Yi-Wen Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/00, H01L23/532, H01L23/538, H01L25/10
CPC Code(s): H01L23/5226
Abstract: provided is a package structure including a die; an electrically connecting structure having a die attach region and a peripheral region surrounding the die attach region, wherein the die is disposed on the electrically connecting structure within the die attach region; an insulating protrusion disposed in the peripheral region and extending in a thickness direction of the die; a conductive structure disposed on the electrically connecting structure and encapsulating the insulating protrusion, wherein the conductive structure is electrically coupled to the electrically connecting structure and the die; and a dielectric structure disposed on the electrically connecting structure and encapsulating the die and the conductive structure.
Inventor(s): Wei-Chen CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chieh LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Ping CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. the substrate includes a semiconductor device. the dielectric layer is disposed on the substrate. the first conductive feature is formed in the first dielectric layer. the second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.
Inventor(s): Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Chen of Zhutian Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/00, H01L23/48, H01L23/528, H01L25/16
CPC Code(s): H01L23/5226
Abstract: a method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.
Inventor(s): Chung-Liang CHENG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Shih Wei BIH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/3105, H01L21/311, H01L21/768
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
Inventor(s): Hui Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Sheh Huang of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Jen Hung Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Su-Jen Sung of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien Chi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Hsuan Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (cesls) and interconnects, along with methods for fabrication, are disclosed herein. a method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride cesl over the copper interconnect and the dielectric layer. an interface between the metal nitride cesl and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. a nitrogen plasma treatment is performed to modify the interface between the metal nitride cesl and the copper interconnect. the nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.
Inventor(s): Hung-Jen Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, G06F30/3953, H01L23/00
CPC Code(s): H01L23/528
Abstract: a semiconductor device is manufactured by a process including identifying a course extending between a minimum distance between a first perimeter of a first conductive pad and a second perimeter of a second conductive pad. the process can include forming a first conductive trace crossing the identified course. the first conductive trace can extend along a direction perpendicular to the course.
20240379546. Via Structures_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/02, H01L21/768, H01L23/522, H01L23/532, H01L23/535, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L23/5283
Abstract: a device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. the fin includes a stack of channel layers engaged by the gate stack. the source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. a ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.
Inventor(s): Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong Ni of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/5283
Abstract: a semiconductor device includes a patterned wiring layer disposed above a semiconductor substrate, the patterned wiring layer including a plurality of wiring portions, and adjacent wiring portions being separated from each other. the semiconductor device also includes a first insulating passivation layer disposed over the wiring portions in a region between adjacent wiring portions, the first insulating passivation layer having a horizontal surface in the region between adjacent wiring portions. the semiconductor device further includes a second insulating passivation layer disposed on the first insulating passivation layer. the first insulating passivation layer and the second insulating passivation layer do not have a void in the region between adjacent wiring lines.
Inventor(s): Hung-Chung Chien of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hong Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Feng Shieh of Tainan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/02, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L23/5286
Abstract: a semiconductor structure includes channel structures vertically stacked, a gate structure engaging the channel structures, an epitaxial feature abutting the channel structures, a backside interconnect layer disposed under the epitaxial feature, and a backside metal contact disposed directly under the epitaxial feature and electrically coupling the epitaxial feature to the backside interconnect layer. in a cross-sectional view of the semiconductor structure along a lengthwise direction of the channel structures, the backside metal contact extends to a position directly under the channel structures.
Inventor(s): Wan-Yu LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Shen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Nan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Xiang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Tien KAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhih-Hong YE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/522
CPC Code(s): H01L23/5286
Abstract: various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. some or all of the conductive interconnects are included in a power delivery system. in general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
Inventor(s): Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/48, H01L23/522
CPC Code(s): H01L23/5286
Abstract: apparatus and methods for back side routing a data signal in a semiconductor device are described. in one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.
Inventor(s): Chen-Hung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsun Wang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Hsuan Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien Chi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Kui Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L29/417
CPC Code(s): H01L23/53238
Abstract: a semiconductor device includes a source/drain component of a transistor. a source/drain contact is disposed over the source/drain component. a source/drain via is disposed over the source/drain contact. the source/drain via contains copper. a first liner at least partially surrounds the source/drain via. a second liner at least partially surrounds the first liner. the first liner and the second liner are disposed between the source/drain contact and the source/drain via. the first liner and the second liner have different material compositions.
Inventor(s): Chia-Yang Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shiu-Ko JangJian of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chun Wang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Si Yu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/311, H01L21/3213, H01L21/768, H01L29/417
CPC Code(s): H01L23/53266
Abstract: a semiconductor device includes a transistor having a source/drain and a gate. the semiconductor device also includes a conductive contact for the transistor. the conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. the conductive contact includes a plurality of barrier layers. the barrier layers have different depths from one another.
Inventor(s): Shu-Wei LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen CHAN of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi YANG of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53276
Abstract: an interconnection structure, along with methods of forming such, are described. the interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. the first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. the structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. the structure further includes a dielectric material disposed between the first and second portions of the conductive layer.
Inventor(s): Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen Chan of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/522
CPC Code(s): H01L23/53276
Abstract: a semiconductor structure is provided. the semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ild) layer. the semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. an etch-stop layer (esl) is horizontally interposed between the first graphene layer and the second graphene layer. a side surface of the first or the second graphene layer directly contacts a side surface of the esl. a third conductive feature is electrically coupled to the second conductive feature. the third conductive feature is separated from the first graphene layer by a portion of the esl, and the third conductive feature also directly contacts a top surface of the esl.
Inventor(s): Shao-Kuan LEE of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw TSAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin LEE of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hsiaokang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/522, H01L23/535, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/45, H01L29/775, H01L29/786
CPC Code(s): H01L23/53276
Abstract: an interconnection structure, along with methods of forming such, are described. the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.
Inventor(s): Gulbagh Singh of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Tsang Chuang of Miaoli City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Jen Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/74, H01L21/768, H01L23/482, H01L23/485, H01L23/522, H01L23/532, H01L27/12
CPC Code(s): H01L23/535
Abstract: the present disclosure describes a method for reducing rc delay in radio frequency operated devices or devices that would benefit from an rc delay reduction. the method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.
Inventor(s): Wei-An Tsao of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen Yu Wu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L25/065
CPC Code(s): H01L23/5383
Abstract: embodiments include a method for forming an integrated circuit package. a first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. a first metallization pattern is formed extending along and through the first dielectric layer. a second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. the second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. after the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. the wafer and the first dielectric layer are sawed in the scribe line region.
Inventor(s): Chih-Hang Tung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Su-Chun Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Lin Shih of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/50, H01L21/768, H01L23/373, H01L25/065
CPC Code(s): H01L23/5384
Abstract: a manufacturing method of a semiconductor device includes the following steps. an electrical insulating and thermal conductive layer is formed over a semiconductor substrate. a dielectric structure is formed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. an opening is formed in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer. a circuit layer is formed in the dielectric structure, wherein the circuit layer fills the opening.
Inventor(s): Xin-Hua Huang of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Ming Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/768, H01L23/00, H01L23/48, H01L29/778
CPC Code(s): H01L23/5384
Abstract: various embodiments of the present disclosure are directed towards an integrated circuit (ic) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. an interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (imd) layer. the imd layer is bonded to the top of the semiconductor substrate and accommodates a pad. a semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. the semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. the dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. a contact extends through the semiconductor layer to the pad.
Inventor(s): Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Techi WONG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao TSAI of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao CHUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L25/00, H01L25/10
CPC Code(s): H01L23/5389
Abstract: a method for forming a chip package structure is provided. the method includes forming a conductive pillar in a substrate layer, forming a recess in the substrate layer, disposing a chip in the recess, forming a molding layer in the recess and surrounding the chip. and forming a redistribution structure over the substrate layer and electrically connecting the conductive pillar to the chip.
Inventor(s): Jen-Yuan CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/552
CPC Code(s): H01L23/552
Abstract: a semiconductor device includes an inductance structure and a shielding structure. the shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. the shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.
Inventor(s): Chih-Hsiang Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Feng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Jen Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Hsu of Chung-Ho City (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Seng Shue of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hong Cha of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Yi Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/02, H01L21/48, H01L23/31, H01L23/522, H01L23/532
CPC Code(s): H01L23/585
Abstract: a semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
Inventor(s): Jen-Yuan CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/768, H01L23/48
CPC Code(s): H01L23/585
Abstract: some implementations described herein provide an electronic device. the electronic device includes a first conductive structure that extends through a dielectric structure of the electronic device and into a substrate of the electronic device. the electronic device includes a guard ring, having multiple layers, that extends along one or more sides of a first vertical portion of the first conductive structure. the electronic device includes a second conductive structure that extends along a second vertical portion of the first conductive structure, where the second conductive structure includes a conductive structure side surface, which is nearest to a side surface of the first conductive structure, that is a distance from the side surface of the first conductive structure, and where the distance is greater than or equal to approximately 5% of a width of the first conductive structure.
Inventor(s): Yen Lian LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/71, H01L23/00
CPC Code(s): H01L23/585
Abstract: integrated circuit (ic) chips and seal ring structures are provided. an ic chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.
Inventor(s): Min-Feng Ku of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chun Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chien Li of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Pin Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/768, H01L23/48
CPC Code(s): H01L23/585
Abstract: integrated circuit (ic) structures and methods for forming the same are provided. an ic structure according to the present disclosure includes a substrate, an interconnect structure over the substrate, a guard ring structure disposed in the interconnect structure, a via structure vertically extending through the guard ring structure, and a top metal feature disposed directly over and in contact with the guard ring structure and the via structure. the guard ring structure includes a plurality of guard ring layers. each of the plurality of guard ring layers includes a lower portion and an upper portion disposed over the lower portion. sidewalls of the lower portions and upper portions of the plurality of guard ring layers facing toward the via structure are substantially vertically aligned to form a smooth inner surface of the guard ring structure.
Inventor(s): Hsiu-Ying Cho of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L21/768, H01L23/528, H01L27/06, H01P3/00, H01P3/08
CPC Code(s): H01L23/66
Abstract: an exemplary device includes a dielectric layer and a transmission line structure disposed in the dielectric layer. the transmission line structure includes a first metal line disposed between a second metal line and a third metal line. dielectric islands are disposed in a first region and a second region of the dielectric layer. the first region of the dielectric layer is between the first metal line and the second metal line. the second region of the dielectric layer is between the first metal line and the third metal line. a dielectric constant of the dielectric islands is greater than a dielectric constant of the dielectric layer. the dielectric islands may be doped sections of the dielectric layer. in some embodiments, the dielectric islands in the first region are aligned with the dielectric islands in the second region along a direction perpendicular to a lengthwise direction of the first metal line.
Inventor(s): Kuo-An Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chiung Tu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Yang Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai Tak Lam of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/02
Abstract: methods and semiconductor structures are provided. a semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. a space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.
Inventor(s): Tzu-Hsuan Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chern-Yow Hsu of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/308
CPC Code(s): H01L24/03
Abstract: the present disclosure, in some embodiments, relates to an integrated chip. the integrated chip includes a conductive feature disposed over a dielectric structure on a substrate. a first layer is arranged on peripheral regions of the conductive feature. a second layer has a bottommost surface arranged on the first layer. the second layer includes a material that etches at a higher rate than the first layer when exposed to a first etchant and that etches at a lower rate than the first layer when exposed to a second etchant. an additional conductive feature extends through the first layer and the second layer to contact the conductive feature.
Inventor(s): Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wen Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fang-I Chih of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ling Chang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/311, H01L21/321, H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L24/05
Abstract: a method includes providing a workpiece having a first conductive pad and a second conductive pad over a substrate, a topmost point of the second conductive pad is above that of the first conductive pad by a height difference, conformally forming a first etch stop layer on the first and the second conductive pads, forming a dielectric structure over the first etch stop layer, performing a planarization process to the dielectric structure, and after the performing of the planarization process, conformally depositing a dielectric layer over the workpiece, the dielectric layer including a first portion disposed directly over the first conductive pad and a second portion disposed directly over the second conductive pad, where a thickness difference between a thickness of the first portion of the dielectric layer and a thickness of the second portion of the dielectric layer is less than the height difference.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/538
CPC Code(s): H01L24/05
Abstract: a package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.
Inventor(s): Chien-Yuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang Ku of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/36, H01L23/522
CPC Code(s): H01L24/08
Abstract: an integrated circuit package includes first and second dies bonded to each other. the first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. the second die includes second bonding pads. the first one of the first bonding pads is connected to a first one of the second bonding pads. the second one of the first bonding pads is connected to a second one of the second bonding pads.
Inventor(s): Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih Ting Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/29, H01L23/31, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: in an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second young's modulus, the first young's modulus less than the second young's modulus.
Inventor(s): Po-Han Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Peng Tai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., I-Chia Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/20
Abstract: a semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. the insulating layer is disposed over the semiconductor device. the redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. the redistribution layer includes a conductive line portion. the semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.
Inventor(s): Chun-Liang LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lin CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao CHOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/73
Abstract: some implementations described herein provide a semiconductor structure. the semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. the semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. the semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Feng Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chuan-An Cheng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/78, H01L25/00, H01L25/065
CPC Code(s): H01L24/80
Abstract: in a method, a wafer is bonded to a first carrier. the wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. the method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. the electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.
Inventor(s): Han-De Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-I Chu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yun Chen Teng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Cherng Sheu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/66
CPC Code(s): H01L24/94
Abstract: a method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. a bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. when the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.
Inventor(s): Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Ju Tsou of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L21/66, H01L21/78, H01L23/544
CPC Code(s): H01L24/96
Abstract: a shift control method in manufacture of semiconductor device includes: calculating a difference of a relative position between a conductive connector of a semiconductor die and a conductive pad of the semiconductor die relative to a reference mark on the semiconductor die; placing the semiconductor die over a carrier, wherein the difference is compensated when placing the semiconductor die over the carrier; and forming a lithographic pattern on the conductive connector of the semiconductor die.
Inventor(s): Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/48, H01L23/544
CPC Code(s): H01L25/0652
Abstract: a package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. the integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Ling Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L23/00, H01L23/48, H01L25/00
CPC Code(s): H01L25/0655
Abstract: in an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.
Inventor(s): Ying-Ju Chen of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor structure includes a bottom die, a top die bonded to the bottom die and including a through substrate via, an insulating layer disposed on the bottom die and laterally covering the top die, a first die connector overlying the insulating layer and the top die, and a second die connector overlying the top die and connected to the through substrate via of the top die. a bonding interface of the top and bottom dies is substantially flat, and the first die connector is inserted into the insulating layer to be in electrical and physical contact with the bottom die.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tin-Hao Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L25/00, H01L25/18
CPC Code(s): H01L25/105
Abstract: a package includes a building block. the building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. the package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. the interconnect structure has redistribution lines electrically coupling to the device die. a power module is over the interconnect structure. the power module is electrically coupled to the building block through the interconnect structure.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/48, H01L21/56, H01L23/14, H01L23/31, H01L23/498, H01L23/538, H01L25/00
CPC Code(s): H01L25/105
Abstract: some embodiments relate to a package. the package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. the first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. the interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. the interposer frame includes a plurality of through substrate holes (tshs) which pass entirely through the interposer frame. a tsh is aligned with the first and second connection pads, and solder extends through the tsh to electrically connect the first connection pad to the second connection pad.
Inventor(s): Heh-Chang HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Jen LI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Haw TSAO of Tai-chung (TW) for taiwan semiconductor manufacturing company, ltd., Shyue-Ter LEU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/00
CPC Code(s): H01L25/16
Abstract: a method of forming a semiconductor device package is provided, including bonding passive devices to a first surface of a package substrate; forming a first underfill element on the first surface to surround the passive devices; forming a first molding layer to encapsulate the passive devices and the first underfill element; bonding a die to a second surface of the package substrate; forming a second underfill element on the second surface to surround the die; forming a second molding layer to encapsulate the die and the second underfill element; forming openings in the second molding layer to expose contact pads formed on the second surface of the package substrate; and disposing conductive bumps in the openings to electrically contact the contact pads, wherein the conductive bumps is in direct contact with the second surface and exposed from the second molding layer.
Inventor(s): Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/48, H01L23/00, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: a method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.
Inventor(s): Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Techi Wong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuo-Mao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Wei Chou of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/065, H01L27/01
CPC Code(s): H01L25/18
Abstract: an embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.
Inventor(s): Chang-Yi Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/48, H01L21/683, H01L23/498, H01L23/538, H01L25/00, H01L25/16
CPC Code(s): H01L25/18
Abstract: a method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.
Inventor(s): Tun-Jen Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Heng Hsieh of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Bao-Ru Young of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/398, H01L21/8234, H01L21/8238, H01L27/092, H10B10/00
CPC Code(s): H01L27/0207
Abstract: an integrated circuit (ic) layout design is received that includes a first circuit cell and a second circuit cell abutted to one another. the first circuit cell contains a first ic component, and the second circuit cell contains a second ic component. a determination is made that a distance between the first ic component and the second ic component is less than a predefined threshold when the first circuit cell and the second circuit cell are abutted together. the ic layout design is revised such that the distance between the first ic component and the second ic component is eliminated in the revised ic layout design.
Inventor(s): Chih-Hao Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/0207
Abstract: the disclosed circuit includes a first and a second active region (ar) spaced a spacing s along a direction in a first standard cell (sc) that spans dalong the direction between a first and a second cell edge (ce). each of the first and second ars spans a first width walong the direction; a third and a fourth ar spaced s in a second sc that spans a second dimension dalong the direction between a third and a fourth ce; and gate stacks extend from the fourth ce of the second sc to the first ce of the first sc, wherein d<d; each of the third and fourth ars spans a second width walong the direction; w<w; and the third ce is aligned with and contacts the second ce. the first and second ars have a structure different from the third and fourth ars.
Inventor(s): Yi Ching Ong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuen-Yi Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsuan Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L23/495, H01L23/538
CPC Code(s): H01L27/0617
Abstract: the present disclosure relates to an integrated chip including a first metal layer over a substrate. a second metal layer is over the first metal layer. an ionic crystal layer is between the first metal layer and the second metal layer. a metal oxide layer is between the first metal layer and the second metal layer. the first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
Inventor(s): Kai-Qiang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chun Fu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng Yuan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L21/265, H01L29/66, H01L29/78
CPC Code(s): H01L27/0629
Abstract: a method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.
Inventor(s): Cheng-Chien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Wen Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Horng-Huei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chiang of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/06, H01L21/306, H01L21/762, H01L21/8234, H01L21/8238, H01L23/528, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L27/0629
Abstract: a semiconductor device includes a finfet component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the finfet component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the finfet component. a height of the patterned dummy semiconductor fins is shorter than that of the fins of the finfet component.
Inventor(s): Yu-Chang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia YEO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L27/088
Abstract: an integrated circuit includes a substrate, a well formed over a portion of the substrate, a stacked structure formed over a first portion of the well, a doped epi structure formed over a second portion of the well adjacent the stacked structure and below a plane defined by an upper surface of the first portion of the well, and a source/drain region formed over the doped epi structure.
Inventor(s): Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Tsai of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hsien Liu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chih Yuan of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jhu-Min Song of Nantou City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: some embodiments relate to an integrated chip structure. the integrated chip structure includes a substrate having a first device region and a second device region. a plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. the epitaxial source/drain regions have an epitaxial material. a plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. a dummy region includes one or more dummy structures. the one or more dummy structures have dummy epitaxial regions including the epitaxial material.
Inventor(s): Chi-Wei Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: a semiconductor device includes a silicon substrate and a fin formed above the substrate. the fin provides active regions for two devices, such as gate-all-around transistors. the semiconductor device also includes a fin-insulating structure positioned to electrically isolate the active regions for the two devices. the fin-insulating structure is formed in a trench, with a first portion adjacent the fin and a second portion below the fin and extending into the substrate. the fin-insulating structure includes an oxide liner in the second portion of the trench, but not the first portion. the fin-insulating structure is further filled with an insulating material such as silicon nitride.
Inventor(s): Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/088
Abstract: semiconductor devices and method of forming the same are provided. in one embodiment, a semiconductor device includes a first transistor and a second transistor. the first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. the second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.
Inventor(s): Shahaji B. More of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (fets) or gate-all-around (gaa) fets, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. an exemplary source/drain structure extends from a topmost channel layer to a depth into a semiconductor substrate. the source/drain structure includes an undoped epitaxial layer with a trough-shaped top surface, a first doped epitaxial layer over the undoped epitaxial layer, a second doped epitaxial layer over the first epitaxial layer, and a third doped epitaxial layer over the second doped epitaxial layer. a thickness of the undoped epitaxial layer is less than the depth of the epitaxial source/drain structure into the semiconductor substrate. the thickness and the depth are tuned based on a size of an active region to which the epitaxial source/drain structure belongs, such that the epitaxial source/drain structure mitigates short channel effects while optimizing performance.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Tuo HUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Shiuan TSAIR of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/28, H01L21/8234, H01L29/40, H01L29/423, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: the present disclosure describes a method for forming (i) input/output (i/o) fin field effect transistors (fet) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-i/o fets with metal gate electrodes and high-k gate dielectrics. the method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. the method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.
Inventor(s): Chi-Sheng Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chung Sun of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Ting Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. a gate structure is disposed over the fin structures. the gate structure extends in a second direction in the top view. the second direction is different from the first direction. the fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. an end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. the end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.
Inventor(s): Chia-Ta Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L29/06, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (s/d) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the s/d features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.
Inventor(s): Chih-Hsin Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/308, H01L29/06
CPC Code(s): H01L27/0886
Abstract: semiconductor structures and fabrication processes are provided. a semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. the second region includes a fourth fin and a fifth fin extending along the first direction. the first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. the third fin terminates at an interface between the first region and the second region.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/08, H01L29/10, H01L29/165, H01L29/167, H01L29/417, H01L29/423, H01L29/49, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a method of forming a semiconductor device includes doping a substrate with a dopant to form a first well region of a first circuit and a second well region of a second circuit, forming first and second active regions respectively over the first and second well regions, forming a first gate stack engaging the first active region and a second gate stack engaging the second active region, and forming a first source/drain (s/d) feature adjoining the first active region and a second s/d feature adjoining the second active region. the first gate stack has a gate pitch less than the second gate stack. the first s/d feature has a depth smaller than the second s/d feature.
Inventor(s): Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chieh Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/092
Abstract: a semiconductor structure and a method of forming the same are provided. in an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. the third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. the dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.
Inventor(s): Kai-Hsuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Cheras (MY) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/768, H01L21/8234, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: a method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ild) layer; forming a trench in the first ild layer adjacent to the fin; filling the trench with a first dummy material; forming a second ild layer over the first ild layer and the first dummy material; forming an opening in the first ild layer and the second ild layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ild layer.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. an exemplary integrated circuit (ic) comprises a first cell including one or more first type gate-all-around (gaa) transistors located in a first region of the integrated circuit; a second cell including one or more second type gaa transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type gaa transistors are one of nanosheet transistors or nanowire transistors and the second type gaa transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (finfets) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.
Inventor(s): Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chandrashekhar Prakash Savant of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: in an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.
Inventor(s): Yu-Hung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Ta Wu of Shueishang Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei Liu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yeur-Luen Tu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chun Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L21/762, H01L21/763, H01L29/06
CPC Code(s): H01L27/1203
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. the semiconductor device is disposed on a frontside of a substrate. the polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. the first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. the substrate includes a monocrystalline facet arranged between the first and second insulator liners. a top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
Inventor(s): Yu-Hung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching I Li of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao Chiang of Jhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Eugene I-Chun Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chia Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14603
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a sensor semiconductor layer. the sensor semiconductor layer is doped with a first dopant. a photodetector is along a frontside of the sensor semiconductor layer. a backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. the backside semiconductor layer is doped with a second dopant. a diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. the diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.
Inventor(s): Ming Chyi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Shu Huang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14607
Abstract: in some embodiments, the present disclosure relates to an image sensor, including a semiconductor substrate, a plurality of photodiodes disposed within the semiconductor substrate, and a deep trench isolation structure separating the plurality of photodiodes from one another and defining a plurality of pixel regions corresponding to the plurality of photodiodes. the plurality of pixel regions includes a first pixel region sensitive to a first region of a light spectrum, a second pixel region sensitive to a second region of the light spectrum, and a third pixel region sensitive to a third region of the light spectrum. the first pixel region is smaller than the second pixel region or the third pixel region.
Inventor(s): Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chieh Chiang of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kung Chang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L31/107
CPC Code(s): H01L27/14625
Abstract: the present disclosure relates to an integrated chip including a substrate and a pixel. the pixel includes a photodetector. the photodetector is in the substrate. the integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. the first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. the outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chang Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Han Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: a metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. one or more conductive structures directly couple the metal grid to a contact pad. the conductive structures may bypass a front side of the image sensor. a bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Chi Hung of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: a semiconductor device includes a substrate having a front side and a back side opposite to each other. a plurality of photodetectors is disposed in the substrate within a pixel region. an isolation structure is disposed within the pixel region and between the photodetectors. the isolation structure includes a back side isolation extending from the back side of the substrate to a position in the substrate. a conductive plug structure is disposed in the substrate within a periphery region. a conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. a conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.
Inventor(s): Cheng-Ta Wu of Shueishang Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hwa Tzeng of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yeur-Luen Tu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: the present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (bdti) structure, and an associated method of formation. in some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. the photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. a bdti structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. the bdti structure comprises a doped liner with the second doping type and a dielectric fill layer. the doped liner lines a sidewall surface of the dielectric fill layer.
Inventor(s): Yu-Hung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Tsung Kuo of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jiech-Fun Lu of Madou Township (TW) for taiwan semiconductor manufacturing company, ltd., Min-Ying Tsai of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chiao-Chun Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching I Li of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: the present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (bdti) structure, and an associated method of formation. in some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. the photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. a bdti structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. the bdti structure comprises a doped liner with the second doping type and a dielectric fill layer. the doped liner lines a sidewall surface of the dielectric fill layer.
Inventor(s): Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chieh Chiang of Yuanlin Township (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hau Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kung Chang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: some embodiments relate to a cmos image sensor disposed on a substrate. a plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. a boundary deep trench isolation (bdti) structure is disposed at boundary regions of the pixel regions, and includes a first set of bdti segments extending in a first direction and a second set of bdti segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. the bdti structure comprises a first material. a pixel deep trench isolation (pdti) structure is disposed within the bdti structure and overlies the photodiode. the pdti structure comprises a second material that differs from the first material, and includes a first pdti segment extending in the first direction such that the first pdti segment is surrounded by the bdti structure.
Inventor(s): Sin-Yao Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ling Shih of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ming Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Wen Hsu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14632
Abstract: various embodiments of the present disclosure are directed towards an integrated circuit (ic) chip comprising a stilted pad structure. a wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. further, a trench isolation structure extends into the frontside of the semiconductor substrate. the stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. the stilted pad structure comprises a pad body and a pad protrusion. the pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. the pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.
Inventor(s): Seiji Takahashi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: various embodiments of the present disclosure are directed towards an image sensor. the image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. a transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. a second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. a readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. a first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.
Inventor(s): Sheng-Chan Li of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yi Hsiao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Che Wei Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L21/768
CPC Code(s): H01L27/1464
Abstract: various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. a plurality of photodetectors is disposed in the semiconductor substrate. an isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. the isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. the metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.
Inventor(s): Po-Chun Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Eugene Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14643
Abstract: in some embodiments, a semiconductor device is provided. the semiconductor device includes an epitaxial structure disposed on a semiconductor substrate. a photodetector is disposed at least partially in the epitaxial structure. a first capping layer is disposed on the semiconductor substrate and covers the epitaxial structure. a second capping layer is disposed vertically between the first capping layer and the epitaxial structure. the first capping layer extends laterally past outermost sidewalls of the epitaxial structure and the second capping layer.
Inventor(s): Po-Chun Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Eugene I-Chun Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L31/028
CPC Code(s): H01L27/14683
Abstract: the present disclosure relates an integrated chip structure. the integrated chip structure includes a base substrate having one or more interior surfaces defining a recess within an upper surface of the base substrate. an epitaxial material is disposed within the recess. a first doped photodiode region is disposed within the epitaxial material and has a first doping type. a second doped photodiode region is disposed within the epitaxial material and has a second doping type. the second doped photodiode region laterally surrounds the first doped photodiode region. a doped epitaxial layer is disposed horizontally and vertically between the base substrate and the epitaxial material. the doped epitaxial layer has the second doping type.
Inventor(s): Chi-Ming LU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Hsiang LIANG of Shinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chan LI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chih TSAO of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hui HUANG of Shinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L21/285, H01L21/3205, H01L21/3213
CPC Code(s): H01L27/14685
Abstract: a method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. the second film stress type is different than the first film stress type. the second film stress intensity is about same as the first film stress intensity. the second film compensates stress induced effect of non-flatness of the substrate by the first film.
Inventor(s): Szu-Hsien Lo of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chung Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522
CPC Code(s): H01L28/24
Abstract: various embodiments of the present disclosure are directed towards an integrated chip (ic). the ic comprises a substrate. a resistor overlies the substrate. the resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. a first dielectric structure is disposed over the substrate and the resistor.
Inventor(s): Tsung-Chieh HSIAO of Shetou Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Yang HSIAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Yao LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L27/08, H10B12/00
CPC Code(s): H01L28/75
Abstract: a semiconductor device includes a metal-insulator-metal (mim) capacitor. the mim capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes. the mim capacitor is disposed in an interlayer dielectric (ild) layer disposed over a substrate. the one or more first electrodes are connected to a side wall of a first via electrode disposed in the ild layer, and the one or more second electrodes are connected to a side wall of a second via electrode disposed in the ild layer. in one or more of the foregoing or following embodiments, the one or more insulating layers include a high-k dielectric material.
Inventor(s): Wei-Ting CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao TSAI of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/50
CPC Code(s): H01L28/91
Abstract: a package structure and a formation method are provided. the method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. the method also includes forming a conductive bonding structure in the dielectric layer. a top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. the conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. the method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
Inventor(s): Chih-Wei Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lin Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kang-Min Kuo of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/28, H01L29/66, H01L29/78
CPC Code(s): H01L29/0607
Abstract: structures and formation methods of a semiconductor device structure are provided. the semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. the gate stack includes a gate dielectric layer and a work function layer. the gate dielectric layer is between the semiconductor substrate and the work function layer. the semiconductor device structure also includes a halogen source layer. the gate dielectric layer is between the semiconductor substrate and the halogen source layer.
Inventor(s): Ko-Cheng Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Lung Cheng of Kaohsiung County (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L23/522, H01L27/092, H01L29/66
CPC Code(s): H01L29/0649
Abstract: a semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.
Inventor(s): Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L27/118
CPC Code(s): H01L29/0649
Abstract: in some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. the first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. a first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. the second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. a second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. the integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.
Inventor(s): Jen-Yuan Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jheng-Hong Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Long Song Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/10, H01L29/78
CPC Code(s): H01L29/0649
Abstract: a method of forming a semiconductor structure including a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.
Inventor(s): Kuo-Chiang Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/66
CPC Code(s): H01L29/0649
Abstract: a semiconductor device includes a gate disposed over a substrate. a source/drain is disposed in the substrate. a conductive contact is disposed over the source/drain. an air spacer is disposed between the gate and the conductive contact. a first component is disposed over the gate. a second component is disposed over the air spacer. the second component is different from the first component.
Inventor(s): Kuan-Kan Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L25/07, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0653
Abstract: bonding and isolation techniques for stacked device structures are disclosed herein. an exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. the bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. the isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. the method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. the first insulation layer and the second insulation layer may include the same or different materials.
Inventor(s): Yen-Yu CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang CHENG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L29/0653
Abstract: the present disclosure is directed to gate-all-around (gaa) transistor structures with a low level of leakage current and low power consumption. for example, the gaa transistor includes a semiconductor layer with a first source/drain (s/d) epitaxial structure and a second s/d epitaxial structure disposed thereon, where the first and second s/d epitaxial structures are spaced apart by semiconductor nano-sheet layers. the semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second s/d epitaxial structures. the gaa transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.
Inventor(s): Guan-Lin Chen of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chien Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.
Inventor(s): Yu-Chang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hung Wu of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: a method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.
Inventor(s): Yi-Ruei JHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: a device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. a first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. a first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786, H10B10/00
CPC Code(s): H01L29/0665
Abstract: some implementations described herein provide a semiconductor device and methods of formation. the semiconductor device may include one or more device types, such as a static random access memory device type, a ring oscillator device type, and/or an input/output device type. a device type may include an n-type metal oxide semiconductor nanostructure transistor and a p-type metal oxide semiconductor nanostructure transistor. in such a case, nanostructure channels of the n-type metal oxide semiconductor nanostructure transistor may have a width that is lesser relative to a width of nanostructure channels of the p-type metal oxide semiconductor nanostructure transistor. additionally, or alternatively, other properties of the nanostructure transistors, such as a gate length or a width of a source/drain region, may vary based on the device type.
Inventor(s): Tzu-Ging Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shun-Hui Yang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chen Yen Ju of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yun-Chen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Liang Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/3065, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: devices with metal structures formed with seams and methods of fabrication are provided. an exemplary method includes forming a metal plug having a top surface formed with a seam; depositing a film over the top surface of the metal plug and at least partially filling the seam; and etching the film from over the metal plug, wherein the film remains in the seam.
Inventor(s): Hsiao-Chun CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Jie SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: the present disclosure describes a semiconductor device with counter-doped nanostructures and a method for forming the semiconductor device. the method includes forming a fin structure on a substrate, the fin structure including one or more first-type nanostructures and one or more second-type nanostructures. the method further includes forming a polysilicon structure over the fin structure and forming a source/drain (s/d) region on a portion of the fin structure and adjacent the polysilicon structure, the s/d region including a first dopant. the method further includes doping the one or more second-type nanostructures with a second dopant via a space released by the polysilicon structure and the one or more first-type nanostructures, where the second dopant is opposite to the first dopant. the method further includes replacing portions of the one or more doped second-type nanostructures with additional second-type nanostructures.
Inventor(s): Jaw-Juinn Horng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Wen Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Ho Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yu Lai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Chow Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L27/088, H01L29/40
CPC Code(s): H01L29/0696
Abstract: a device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. the at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. the at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.
Inventor(s): Wei-Yip LOH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Mao LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Harry CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chin CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhih-Rong HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzer-Min SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/20, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a semiconductor device structure and methods of forming the same are described. in some embodiments, the structure includes an n-type source/drain epitaxial feature disposed over a substrate, a p-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the n-type source/drain epitaxial feature, and a second silicide layer disposed directly on the p-type source/drain epitaxial feature. the first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. the structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. the third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.
Inventor(s): Wei-Yip LOH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Mao LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang HSU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Hsu CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Harry CHIEN of Chandler AZ (US) for taiwan semiconductor manufacturing company, ltd., Chih-Wei CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0847
Abstract: a semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. the first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. the second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. the first metal silicide layer is over one of the first source/drain epitaxy structures. the second metal silicide layer is over one of the second source/drain epitaxy structures. the isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.
Inventor(s): Chih-Ching WANG of Kinmen (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsing HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/768, H01L23/528, H01L23/532, H01L29/06, H01L29/417, H01L29/423
CPC Code(s): H01L29/0847
Abstract: a semiconductor device structure, along with methods of forming such, are described. in one embodiment, a semiconductor device structure is provided. the semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack, wherein each first source/drain feature and second source/drain feature comprises a first side and a second side, and the second side of the first source/drain feature and the back side of the substrate are at different elevations. the semiconductor device structure also includes a conductive feature in contact with the second side of the first source/drain feature, wherein a portion of the back side of the substrate is exposed to air.
Inventor(s): I-Wen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-An Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yuan Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Ren Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Peng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. the method further includes forming an n-type epitaxial source/drain (s/d) feature on the first and second fins, forming a p-type epitaxial s/d feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial s/d feature and the p-type epitaxial s/d feature such that more is removed from the n-type epitaxial s/d feature than the p-type epitaxial s/d feature.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/10, H01L21/02, H01L21/311, H01L21/8238, H01L27/092, H01L29/06, H01L29/16, H01L29/66, H01L29/78
CPC Code(s): H01L29/1054
Abstract: fin-like field effect transistors (finfets) having high mobility strained channels and methods of fabrication thereof are disclosed herein. an exemplary method includes forming a first silicon fin in a first type finfet device region and a second silicon fin in a second type finfet device region. first epitaxial source/drain features and second epitaxial source/drain features are formed respectively over first source/drain regions of the first silicon fin second source/drain regions of the second silicon fin. a gate replacement process is performed to form a gate structure over a first channel region of the first silicon fin and a second channel region of the second silicon fin. during the gate replacement process, a masking layer covers the second channel region of the second silicon fin when a silicon germanium channel capping layer is formed over the first channel region of the first silicon fin.
Inventor(s): Yu-Wen TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ling SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hua YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L29/06, H01L29/423, H01L29/78
CPC Code(s): H01L29/401
Abstract: a method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
Inventor(s): Wei-Han Fan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hua Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/768, H01L29/417, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/401
Abstract: a method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. the method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. the method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. the method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.
Inventor(s): Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chandrashekhar Prakash Savant of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/28, H01L21/8238, H01L27/092, H01L29/49
CPC Code(s): H01L29/401
Abstract: a semiconductor structure includes a first transistor adjacent a second transistor. the first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer. the first and the second gate metal layers include different materials. the semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer. one of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum. a bottom surface of the first gate metal layer is directly on a top surface of the first barrier.
Inventor(s): Fu-Hsiang Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi Hsien Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/8234, H01L23/522, H01L23/535, H01L29/417, H01L29/423
CPC Code(s): H01L29/401
Abstract: a method according to the present disclosure includes receiving a workpiece that includes a first gate structure including a first cap layer thereon, a first source/drain contact adjacent the first gate structure, a second gate structure including a second cap layer thereon, a second source/drain contact, an etch stop layer (esl) over the first source/drain contact and the second source/drain contact, and a first dielectric layer over the esl. the method further includes forming a butted contact opening to expose the first cap layer and the first source/drain contact, forming a butted contact in the butted contact opening, after the forming of the butted contact, depositing a second dielectric layer, forming a source/drain contact via opening through the second dielectric layer, the esl layer, and the first dielectric layer to expose the second source/drain contact, and forming a source/drain contact via in the source/drain contact via opening.
Inventor(s): Meng-Huan Jao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Su of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/311, H01L21/321, H01L29/417, H01L29/45
CPC Code(s): H01L29/401
Abstract: a method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (cmp) process to the metal layer.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Huei Li of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Da-Yuan Lee of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/285, H01L21/3215, H01L21/8234, H01L27/088, H01L29/49
CPC Code(s): H01L29/401
Abstract: a method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I Wu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/28, H01L21/285, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/786
CPC Code(s): H01L29/401
Abstract: a method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. the metal-containing layer and the silicon-containing layer in combination act as a work-function layer. a planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.
Inventor(s): Kuo-Chang Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang Sun of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., TsuChing Yang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/28, G11C11/22, H01L29/51, H01L29/78, H01L29/786
CPC Code(s): H01L29/40111
Abstract: a memory cell includes a thin film transistor over a semiconductor substrate. the thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (os) layer contacting a source line and a bit line, wherein the memory film is disposed between the os layer and the word line; and a dielectric material separating the source line and the bit line. the dielectric material forms an interface with the os layer. the dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the os layer is no more than 3 atomic percent (at %).
Inventor(s): Wei Hao Lu of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of Chubei (TW) for taiwan semiconductor manufacturing company, ltd., Chien-I Kuo of Taibao (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Xuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. the semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. the backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.
Inventor(s): Chung-Wei Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun Chu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/423, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. a bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. the semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.
Inventor(s): Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/4175
Abstract: a method for forming a semiconductor transistor device includes forming a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. the channel structure is formed by forming a stack of semiconductor layers. the gate structure is formed wrapping around the channel structure. the first source/drain epitaxial structure and the second source/drain epitaxial structure are formed on opposite endings of the channel structure. the gate contact is formed on the gate structure. the back-side source/drain contact is formed under the first source/drain epitaxial structure. the second source/drain epitaxial structure is formed to have a concave bottom surface.
Inventor(s): Kuo-Chiang Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Huang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L27/088, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/78, H10B10/00
CPC Code(s): H01L29/41775
Abstract: one or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. a source/drain component is disposed over the one or more active region structures in the vertical direction. a source/drain contact is disposed over the source/drain component in the vertical direction. the source/drain contact includes a bottom portion and a top portion. a protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.
Inventor(s): Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd., Szu-Hsien Liu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chih Yuan of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/762, H01L21/8234, H01L29/40, H01L29/78
CPC Code(s): H01L29/42368
Abstract: in some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. a source region and a drain region are arranged within the substrate on opposite sides of the well region. a gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. a trench isolation structure surrounds the source region, the drain region, and the gate electrode. a gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. the gate electrode structure has a central portion and a corner portion. the central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
Inventor(s): Chen-Liang Chu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chang Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ta Lei of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Hsin Liu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Yuan Kung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L21/285, H01L21/762, H01L29/06, H01L29/08, H01L29/45, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/42376
Abstract: a method to form a transistor device with a recessed gate structure is provided. in one embodiment, a gate structure is formed overlying a device region and an isolation structure. the gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. a pair of source/drain regions in is formed the device region on opposite sides of the gate structure. a sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. a resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
Inventor(s): Bo-Wen Hsieh of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Jia Hsieh of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Lo of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Mi-Hua Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/40, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/42376
Abstract: a semiconductor structure and a method for forming the same are provided. the semiconductor structure includes a gate stack structure formed over a substrate. the gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. in addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.
Inventor(s): Eugene I-Chun Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shiung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao Chiang of Jhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/768, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L29/42384
Abstract: a method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.
Inventor(s): Shen-Yang Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/324, H01L29/06, H01L29/66
CPC Code(s): H01L29/42392
Abstract: a method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer, overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.
Inventor(s): Chia-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Cheng Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hang Chiu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ju Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chih Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chen Hsiao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/40, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. the active region structures each extend in a first horizontal direction. the active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. a gate structure is disposed over the active region structures. the gate structure extends in the second horizontal direction. the gate structure partially wraps around each of the active region structures. a conductive capping layer is disposed over the gate structure. a gate via is disposed over the conductive capping layer. a dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
Inventor(s): Cheng-Wei Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin Liang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/762, H01L27/088, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: in an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.
Inventor(s): Cheng-Ting Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hou-Yu Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/417, H01L29/66
CPC Code(s): H01L29/42392
Abstract: a semiconductor device includes a semiconductor layer, a gate structure, a source/drain epitaxial structure, a backside dielectric cap, and an inner spacer. the gate structure wraps around the semiconductor layer. the source/drain epitaxial structure is adjacent the gate structure and electrically connected to the semiconductor layer. the backside dielectric cap is disposed under and in direct contact with the gate structure. the inner spacer is in direct contact with the gate structure and the backside dielectric cap.
Inventor(s): Chao-Ching Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Tse Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jin Cai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/20, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. the sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. the method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.
Inventor(s): Chia-Hao Pao of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/265, H01L21/308, H01L29/06, H01L29/40, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first sige layer and a stack alternating si layers and second sige layers disposed over the first sige layer and the first sige layer has a first concentration of ge and each of the second sige layers has a second concentration of ge that is greater than the first concentration, recessing the fin to form an s/d recess, recessing the first sige layer and the second sige layers exposed in the s/d recess, where the second sige layers are recessed more than the first sige layer, forming an s/d feature in the s/d recess, removing the recessed first sige layer and the second sige layers to form openings, and forming a metal gate structure over the fin and in the openings.
Inventor(s): Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Choh Fei Yeap of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Da-Wen Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a first gate-all-around (gaa) transistor is formed on the first fin structure; the first gaa transistor has a channel region within a first plurality of nanostructures. a second gaa transistor is formed on the second fin structure; the second gaa transistor has a second channel region configuration. the second gaa transistor has a channel region within a second plurality of nanostructures. the second plurality of nanostructures is less than the first plurality of nanostructures.
Inventor(s): Wei Ju LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. a gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. a first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. an isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.
Inventor(s): Chung-Liang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L27/12
CPC Code(s): H01L29/42392
Abstract: a semiconductor device includes a substrate, a gate all around (gaa) device overlying the substrate, and a thin film transistor (tft) overlying the gaa device, and a passive device overlying the tft. the substrate, the gaa device, the tft, and the passive device is subsequently stacked on each other and at least partially overlap with each other. a via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. the first end of the via is connected to the passive device and the second end of the via is connected to one layer of the gaa device. the middle portion of the via is laterally spaced apart from the tft and the passive device.
Inventor(s): Chia-Ming HSU of Hualien County (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu CHOU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin TSAO of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Yuan HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Huei CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/45, H01L21/02, H01L21/285, H01L21/3205, H01L21/768, H01L21/8234, H01L23/485, H01L23/532, H01L27/088, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L29/45
Abstract: a semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. the first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
Inventor(s): Pei-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/45, H01L21/02, H01L21/285, H01L21/311, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/458
Abstract: a method according to the present disclosure includes providing a workpiece. the workpiece includes a fin-shaped structure including a channel region and a source/drain region, a metal gate structure disposed over the channel region, a dummy source/drain feature disposed over the source/drain region, and a dielectric structure disposed over the dummy source/drain feature. the method further includes forming a trench through the dielectric structure and the dummy source/drain feature to expose a sidewall of the channel region, forming an epitaxial layer over the sidewall of the channel region, and forming a metal feature over a sidewall of the epitaxial layer and in the trench.
Inventor(s): Wen-Shun Lo of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yingkit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/47, H01L29/06, H01L29/66, H01L29/872
CPC Code(s): H01L29/47
Abstract: a semiconductor device includes a substrate having a p-well region, an n-well region disposed on either side of and abutting the p-well region, and a deep n-well region disposed beneath and abutting both the p-well region and at least part of the n-well region on either side of the p-well region. the semiconductor device further includes a first conductive layer formed over a cathode region of the p-well region, where a schottky barrier is formed at a junction of the first conductive layer and the p-well region. the semiconductor device further includes a second conductive layer formed over anode regions of the p-well region, where the anode regions are disposed on either side of the cathode region.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/4908
Abstract: in an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.
Inventor(s): Shih-Hang Chiu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chiang Wu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jo-Chun Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/4908
Abstract: semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. in an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
Inventor(s): Yong-Tian Hou of Singapore (SG) for taiwan semiconductor manufacturing company, ltd., Yuan-Shun Chao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hao Chen of Chuangwei Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/28, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H01L29/4966
Abstract: a semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. the gate electrode includes a first metal layer, a second metal layer, and a third metal layer. the second layer includes metal and oxygen. the first layer is first layer over the gate dielectric layer and may include one of titanium nitride (tin), titanium silicon nitride (tisin), or tantalum carbide (tac). minimization of equivalent oxide thickness may result.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/285, H01L29/40, H01L29/66
CPC Code(s): H01L29/4966
Abstract: a semiconductor device and a method of forming the same are provided. the semiconductor device includes a gate stack over an active region of a substrate. the gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. the first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. the plurality of first layers include a first material. the plurality of second layers include a second material different from the first material.
Inventor(s): Ko-Cheng Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Lung Cheng of Kaohsiung County (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/28, H01L21/764, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/4991
Abstract: a semiconductor structure includes a substrate, a semiconductor fin-shaped structure protruding from the substrate and extending lengthwise along a first direction, an isolation feature disposed over the substrate and adjacent to the semiconductor fin-shaped structure and extending lengthwise along the first direction, a metal gate stack disposed over a channel region of the semiconductor fin-shaped structure and extending lengthwise along a second direction perpendicular to the first direction, a gate spacer disposed along a sidewall of the metal gate stack and along a sidewall of the semiconductor fin-shaped structure, a source/drain feature disposed over a source/drain region of the semiconductor fin-shaped structure and adjacent to the metal gate stack, a dielectric layer disposed over the source/drain feature, and an air gap disposed between the gate spacer and the dielectric layer along the first direction and wrapping around the semiconductor fin-shaped structure.
Inventor(s): Bor Chiuan Hsieh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Jung Ho of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Cheng Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/40, H01L29/417, H01L29/78
CPC Code(s): H01L29/66515
Abstract: a method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. the source/drain region is underlying and exposed to the source/drain contact opening. a source/drain contact plug is formed in the source/drain contact opening. a gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.
Inventor(s): Ko-Cheng Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Lung Cheng of Kaohsiung County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L29/66537
Abstract: multi-gate devices and methods for fabricating such are disclosed herein. an exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (apt) feature in the active region.
Inventor(s): Bwo-Ning CHEN of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Xusheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Miao LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/768, H01L29/06, H01L29/165, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a semiconductor structure includes a p-type metal-oxide semiconductor (pmos) region and an n-type metal-oxide semiconductor (nmos) region, first source/drain (s/d) features in the pmos region and second s/d features in the nmos region, a first channel region connecting the first s/d features and a second channel region connecting the second s/d features, a first high-k metal gate stack (hkmg) over the first channel region and a second hkmg over the second channel region, first gate spacers on sidewalls of the first hkmg and second gate spacers on sidewalls of the second hkmg, a first etch-stop layer (esl) on the first s/d features and the first gate spacers and a second esl on the second s/d features and the second gate spacers, an oxide layer on the first esl but not the second esl, and an interlayer dielectric (ild) layer on the oxide layer and the second esl.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/51, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. the first gate stack is on the active channel region. the gate isolation region separates the first gate stack from the second gate stack.
Inventor(s): Shiang-Bau Wang of Pingzchen City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L27/088, H01L29/78
CPC Code(s): H01L29/66545
Abstract: in a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. the dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. a portion of the dummy gate remains and protects the adjacent structure. a gate electrode can then be formed in the trench. a two step process can be employed, using an initial isotropic etch followed by the directional etch.
Inventor(s): Ming-Jhe Sie of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Huang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Hua Hsu of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Ping Lee of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., An Chyi Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shiang-Bau Wang of Pingzchen City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/768, H01L21/8238, H01L27/092, H01L29/78
CPC Code(s): H01L29/66545
Abstract: in an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ild) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping Chen of Toucheng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/027, H01L21/311, H01L21/762, H01L21/8234, H01L27/088, H01L29/06, H01L29/10, H01L29/423, H01L29/51, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.
Inventor(s): Bone-Fong Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/06, H01L29/423, H01L29/78
CPC Code(s): H01L29/66553
Abstract: a semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. the channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. the first ridge partially extends between the first inner spacer feature and the gate structure.
Inventor(s): Che-Cheng Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chi Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Horng-Huei Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/78
CPC Code(s): H01L29/6681
Abstract: a method includes forming a first active fin structure and a second active fin structure on a substrate. a dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. the dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. a plurality of protruding features is formed on the first portion of the substrate. a shallow trench isolation (sti) region is formed over the first portion of the substrate, the sti region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the sti region.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping Chen of Toucheng Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L27/088, H01L29/06, H01L29/78
CPC Code(s): H01L29/6681
Abstract: a method of fabricating a semiconductor device is disclosed. the method includes forming semiconductor fins on a substrate. a first dummy gate is formed over the semiconductor fins. a recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. a dummy fin material is formed in the recess. a portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. a second dummy gate is formed on the exposed upper surface of the first dummy gate.
Inventor(s): Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu Ang Chao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lain-Jong Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/76, H01L21/02, H01L21/4757, H01L21/8256, H01L23/31, H01L27/092, H01L29/24, H01L29/417, H01L29/45, H01L29/49, H01L29/66, H01L29/786, H10K10/46, H10K10/84, H10K10/88, H10K19/10, H10K85/20
CPC Code(s): H01L29/7606
Abstract: a device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. the work function layer is an n-type work function layer. the device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. the dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.
Inventor(s): Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chen Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chung Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Yi Su of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ku Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuan-Wei Tsou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun Lin Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/778, H01L29/20, H01L29/205, H01L29/40, H01L29/66
CPC Code(s): H01L29/7787
Abstract: the present disclosure provides a semiconductor structure. the semiconductor structure includes a gallium nitride (gan) layer on a substrate; an aluminum gallium nitride (algan) layer disposed on the gan layer; a gate stack disposed on the algan layer; a source feature and a drain feature disposed on the algan layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.
Inventor(s): Chen-Liang CHU of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chih CHIANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Hsin LIU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Yuan KUNG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chuan LIAO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wen YAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ta LEI of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/66, H03K3/356, H03K19/0185
CPC Code(s): H01L29/7833
Abstract: a medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. moreover, the medium voltage transistor may include an n-type lightly-doped source/drain (nldd) region in which an n source/drain region of the medium voltage transistor is included. the light doping in the nldd region enables a threshold voltage (vi) to be reduced while enabling medium voltage operation at the n source/drain region. to reduce the amount of current leakage in the medium voltage transistor due to the light doping in the nldd region, a buffer layer may be included over and/or on a portion of the nldd region under a gate structure of the medium voltage transistor. the nldd region and the thermal region of the medium voltage transistor enables the threshold voltage of the medium voltage transistor while maintaining the same current leakage performance or reducing current leakage in the medium voltage transistor.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L27/088, H01L29/66
CPC Code(s): H01L29/78391
Abstract: an mfmis-fet includes a mosfet having a three-dimensional structure that allows the mosfet to have an effective area that is greater than the footprint of the mfm or the mosfet. in some embodiment, the gate electrode of the mosfet and the bottom electrode of the mfm are united. in some, they have equal areas. in some embodiments, the mfm and the mosfet have nearly equal footprints. in some embodiments, the effective area of the mosfet is much greater than the effective area of the mfm. these structures reduce the capacitance ratio between the mfm structure and the mosfet without reducing the area of the mfm structure in a way that would decrease drain current.
Inventor(s): Kuo-Chang Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang Sun of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., TsuChing Yang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Jiang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, G11C5/06, G11C11/22, H01L21/28, H01L29/51, H01L29/786
CPC Code(s): H01L29/78391
Abstract: a memory cell includes a ferroelectric (fe) material contacting a word line; and an oxide semiconductor (os) layer contacting a source line and a bit line, wherein the fe material is disposed between the os layer and the word line. the os layer comprises: a first region adjacent the fe material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.
Inventor(s): Wilman TSAI of Saratoga CA (US) for taiwan semiconductor manufacturing company, ltd., Ling-Yen YEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/28, H01L21/8234, H01L27/088, H01L29/51, H01L29/66
CPC Code(s): H01L29/78391
Abstract: in a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. the ferroelectric dielectric layer includes an amorphous layer and crystals.
Inventor(s): Kai-Chieh Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Ju Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Yang Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/08
CPC Code(s): H01L29/7843
Abstract: a semiconductor device and a method of forming the same are provided. a semiconductor device according to an embodiment includes a p-type field effect transistor (pfet) and an n-type field effect transistor (nfet). the pfet includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. the net includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
Inventor(s): Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/265, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/7847
Abstract: a semiconductor structure and a method of forming the same are provided. in an embodiment, an exemplary semiconductor method includes forming a fin-shaped structure extending from a substrate, the fin-shaped structure includes a number of channel layers interleaved by a number of sacrificial layers, recessing a source/drain region to form a source/drain opening, performing a pai process to amorphize a portion of the substrate exposed by the source/drain opening, forming a tensile stress film over the substrate, performing an annealing process to recrystallize the portion of the substrate, the recrystallized portion of the substrate includes dislocations, forming an epitaxial source/drain feature over the source/drain opening, and forming a gate structure wrapping around each of the plurality of channel layers. by performing the above operations, dislocations are controllably and intentionally formed and carrier mobility in the number of channel layers may be advantageously enhanced, leading to improved device performance.
Inventor(s): Hsin-Wen Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kuan Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Ta Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/762
CPC Code(s): H01L29/785
Abstract: a semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. the memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. the n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. the memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. from a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. from a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.
Inventor(s): Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Chuan YOU of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lu LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/308, H01L21/768, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a transistor on a substrate, a contact electrically connected to a source/drain feature of the transistor, a first dielectric layer on a gate stack of the transistor, a second dielectric layer on the contact, a gate spacer layer between the gate stack of the transistor and the contact, and a contact liner between the gate spacer layer and the contact. a top of the contact liner is located higher than a bottom surface of the second dielectric layer and lower than a top surface of the second dielectric layer.
Inventor(s): Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/265, H01L21/28, H01L29/06, H01L29/08, H01L29/10, H01L29/423, H01L29/49
CPC Code(s): H01L29/7851
Abstract: a finfet device and a method of forming the same are provided. the method includes forming semiconductor strips over a substrate. isolation regions are formed over the substrate and between adjacent semiconductor strips. a first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. the first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. a second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. the second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. the reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. the fins extend away from topmost surfaces of the isolation regions.
Inventor(s): Chih-Liang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchy City (TW) for taiwan semiconductor manufacturing company, ltd., Charles Chew -Yuen Young of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun Liu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsiung Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lei-Chun Chou of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/768, H01L21/8234, H01L23/48, H01L23/528, H01L23/535, H01L27/088, H01L29/417, H01L29/66
CPC Code(s): H01L29/7851
Abstract: the present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finfets) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. in some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. in these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. however, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. this isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
Inventor(s): Zhi-Chang Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien Ning Yao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/822, H01L21/8234, H01L27/06, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/7855
Abstract: a semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.
Inventor(s): Pei-Hsun Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsiung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/306, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: semiconductor device and the manufacturing method thereof are disclosed herein. an exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.
Inventor(s): Wu-Wei Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/66
CPC Code(s): H01L29/78618
Abstract: in some embodiments, the present disclosure relates to a device. the device includes an active layer arranged over a substrate. a gate electrode is arranged on a first side of the active layer and spaced apart from the active layer by a gate dielectric layer. a passivation structure is arranged on the active layer. a source contact extends through the passivation structure to contact the active layer and a drain contact extends through the passivation structure to contact the active layer. an upper portion of the passivation structure includes silicon carbide.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/764, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: a semiconductor device includes a fin on a substrate extending along a fin direction, a first and a second source/drain features on the fin. the semiconductor device also includes a stack of semiconductor layers over a first portion of the fin and between the first source/drain feature and the second source/drain feature. the semiconductor device further includes a gate structure over the stack of semiconductor layers. the gate structure extends along a gate direction perpendicular to the fin direction. moreover, the gate structure engages with the stack of semiconductor layers. the semiconductor device includes a dielectric layer interposing between the first source/drain feature and the fin along a vertical direction, where the vertical direction is perpendicular to the fin direction and to the gate direction. the dielectric layer interfaces with the first portion of the fin and isolates the first source/drain feature from the first portion of the fin.
Inventor(s): Chung-Hao Cai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Jun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting Fang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hsien Yao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: semiconductor structures and methods are provided. a semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. the contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.
Inventor(s): Shahaji B. More of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: methods and semiconductor structures are provided. a method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.
Inventor(s): Ting-Yeh CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin LIN of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/3065, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/78618
Abstract: a semiconductor device structure and a method for forming a semiconductor device structure are provided. the semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. the semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. a protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. the semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.
Inventor(s): Wu-Wei Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Ting Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Yi Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tzer-Min Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Tien Tung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L27/088, H01L29/423, H01L29/66
CPC Code(s): H01L29/78696
Abstract: the problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. the second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. the dipoles create an electric field that causes a shift in the threshold voltage. the buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.
Inventor(s): Marcus Johannes Henricus VAN DAL of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Gerben DOORNBOS of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Georgios VELLIANITIS of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mauricio MANFRINI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/66
CPC Code(s): H01L29/78696
Abstract: a semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. the channel layer includes an oxide semiconductor material. the source/drain contacts are disposed in electrical contact with the channel layer. the first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.
Inventor(s): Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Tse Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih Hao Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/84, H01L27/12, H01L29/417, H01L29/423
CPC Code(s): H01L29/78696
Abstract: a transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2d) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.
Inventor(s): Jung-Hung CHANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang LIN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Ning YAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Han CHUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Lin CHUANG of Chia-Yi City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/78696
Abstract: a method for forming a semiconductor device structure is provided. the semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. the method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (s/d) recess and a second s/d recess. the method includes forming a first bottom layer in the first s/d recess and a second bottom layer in the second s/d recess, and forming a first dielectric liner layer over the first bottom layer. the method includes forming a first top layer over the first dielectric liner layer, and forming a first s/d structure over the first top layer and a second s/d structure over the second bottom layer.
Inventor(s): Hsiao-Chun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Jie SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/10, H01L29/15, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/78696
Abstract: gaafet threshold voltages are tuned by introducing dopants into a channel region. in a gaafet that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.
Inventor(s): Shi-Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/8234, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/78696
Abstract: a device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. a first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. a first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. a bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. a dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K19/1776, H03K19/20, H10B99/00
CPC Code(s): H03K19/1776
Abstract: structures and methods for the co-optimization of core (logic) devices and sram devices include a semiconductor device having a logic portion and a memory portion. in some embodiments, a logic device is disposed within the logic portion. in some cases, the logic device includes a single fin n-type finfet and a single fin p-type finfet. in some examples, a static random-access memory (sram) device is disposed within the memory portion. the sram device includes an n-well region disposed between two p-well regions, where the two p-well regions include an n-type finfet pass gate (pg) transistor and an n-type finfet pull-down (pd) transistor, and where the n-well region includes a p-type finfet pull-up (pu) transistor.
Inventor(s): Yun-Wei Cheng of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hao Chou of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Lee of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chi Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04N23/745, H01L27/146, H04N23/73
CPC Code(s): H04N23/745
Abstract: an image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. the first number is substantially equal to the second number. a light-blocking structure disposed over the first pixels and the second pixels. the light-blocking structure defines a plurality of first openings and second openings through which light can pass. the first openings are disposed over the first pixels. the second openings are disposed over the second pixels. the second openings are smaller than the first openings. a microcontroller is configured to turn on different ones of the second pixels at different points in time.
Inventor(s): Ting-Jung Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04R17/00, B81B3/00, B81C1/00, H04R7/04, H04R31/00
CPC Code(s): H04R17/00
Abstract: various embodiments of the present disclosure are directed towards a microelectromechanical systems (mems) device in which a slit at a movable mass of the mems device has a top notch slit profile. the mems device may, for example, be a speaker, an actuator, or the like. the slit extends through the movable mass, from top to bottom, and has a width that is uniform, or substantially uniform, from the bottom of the movable mass to proximate the top of movable mass. further, in accordance with the top notch slit profile, top corner portions of the mems substrate in the slit are notched, such that a width of the slit bulges at the top of the movable mass. the top notch slit profile may, for example, increase the process window for removing an adhesive from the slit while forming the mems device.
Inventor(s): Ting-Ya CHENG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Lin CHANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Lung CHANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H05G2/00, G02B7/185, G02B26/06, G02B26/08, G02B27/09, G03F7/00
CPC Code(s): H05G2/008
Abstract: an apparatus for generating extreme ultraviolet (euv) radiation includes a droplet generator configured to generate target droplets. an excitation laser is configured to heat the target droplets using excitation pulses to convert the target droplets to plasma. a deformable mirror is disposed in a path of the excitation laser. a controller is configured to adjust parameters of the excitation laser by controlling the deformable mirror based on a feedback parameter.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C7/12, G11C11/408, G11C11/4096, G11C11/4097
CPC Code(s): H10B10/12
Abstract: semiconductor devices are provided. a first memory cell includes a first pull-down transistor, a first pass-gate transistor, a first pull-up transistor, and a first isolation transistor. a second memory cell includes a second pull-down transistor, a second pass-gate transistor, a second pull-up transistor, and a second isolation transistor. the first and second isolation transistors share a common gate connected to a vdd line. the gates of the first and second pass-gate transistors are connected to a first wl landing pad and a second wl landing pad. the sources of the first and second pass-gate transistors are connected to the first and second bit lines. the vdd line, the first and second wl landing pads, and the first and second bit lines are formed in a first metal layer, and the vdd line, the first and second bit lines are longer than the first and second wl landing pads.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, H01L23/538, H01L27/088, H01L29/78
CPC Code(s): H10B10/12
Abstract: a semiconductor structure includes a first active region and second active region extending lengthwise along a first direction. the first active region includes a first channel region of a first transistor and having a first channel width along a second direction perpendicular to the first direction, a first source/drain terminal of the first transistor and having a first width along the second direction and greater than the first channel width, and a first epitaxial source/drain feature of the first transistor and disposed over the first source/drain terminal. the second active region includes a second channel region of a second transistor and having a second channel width along the second direction, a second source/drain terminal of the second transistor and having a second width along the second direction and greater than the second channel width, and a second epitaxial source/drain feature of the second transistor and over the second source/drain terminal.
Inventor(s): Chih-Yu Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shan-Mei Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chia Liang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Lun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/12
Abstract: a transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. the first gate dielectric layer is disposed over the substrate. the first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. the second gate dielectric layer is disposed over the first gate dielectric layer. the second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. the second dielectric constant is greater than the first dielectric constant. the first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
20240381609. MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a memory device includes a first static random access memory (sram) cell, a second sram cell, and a first metal layer. the first sram cell includes first read-port pass-gate (pg) and pull-down (pd) transistors arranged in a y-direction, and second read-port pg and pd transistors arranged in the y-direction. the first and second read-port pd transistors share a first gate structure extending in an x-direction. the second sram cell includes third read-port pg and pd transistors arranged in the y-direction, and fourth read-port pg and pd transistors arranged in the y-direction. the third and fourth read-port pd transistors share a second gate structure extending in the x-direction. the first metal layer is over the first and second sram cells. the first metal layer includes first and second read bit-line conductors extending in the y-direction and shared by the first and second sram cells.
Inventor(s): Cheng-Yin WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Xiang YOU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: the first semiconductor layer and the second semiconductor layer are above the first semiconductor layer, in which the first and second semiconductor layers are vertically spaced apart from each other. the first and second source/drain epitaxial features are respectively on first and second sides of the first semiconductor layer. the third and fourth source/drain epitaxial features are respectively on first and second sides of the second semiconductor layer and above the first source/drain epitaxial feature. the first, third, and fourth source/drain epitaxial features have a first conductive type, and the second source/drain epitaxial feature has a second conductive type opposite to the first conductive type.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H10B10/125
Abstract: a semiconductor structure includes a substrate and first and second sram cells. the first sram cell includes first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. the first and the second pass-gate transistors have a first channel width. the first and the second pull-down transistors have a second channel width. a ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5. the second sram cell includes third and fourth pull-up transistors, third and fourth pull-down transistors, and third and fourth pass-gate transistors. the third and the fourth pass-gate transistors have a third channel width. the third and the fourth pull-down transistors have a fourth channel width. the third and the fourth channel widths are substantially same. the fourth channel width is larger than the second channel width. the transistors are gaa transistors.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C7/12, G11C8/08, G11C8/16, G11C11/412, G11C11/413, G11C11/419
CPC Code(s): H10B10/18
Abstract: semiconductor devices are provided. a write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. the first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. the second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. the first and second gate structures of the first and second write pass-gate transistors are connected to a write word line landing pad that is connected to the write word line. the first and second read bit lines and the write word line landing pad extend in the first direction in a first metallization layer. the write word line extends in a second direction in a second metallization layer.
Inventor(s): Yun-Feng Kao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C5/06, G11C14/00, H01L21/28, H01L29/417, H01L29/51, H10B51/30, H10B51/40
CPC Code(s): H10B10/18
Abstract: various embodiments of the present application are directed towards an integrated circuit including a plurality of semiconductor devices disposed on a substrate. a dielectric structure overlies the semiconductor devices. a plurality of conductive interconnect elements are disposed within the dielectric structure and are electrically coupled to one or more of the semiconductor devices. a data backup unit overlies the plurality of conductive interconnect elements. the data backup unit includes a first source/drain structure, a second source/drain structure, a channel layer laterally extending over the first and second source/drain structures, a first upper gate structure, and a second upper gate structure. the first and second upper gate structures overlie the channel layer.
Inventor(s): Chung-Liang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B12/00, H01L21/02, H01L21/225, H01L29/06, H01L29/423, H01L29/66, H01L29/786, H01L29/94
CPC Code(s): H10B12/33
Abstract: a device includes a substrate. a first nanostructure is over the substrate, and includes a semiconductor having a first resistance. a second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. a first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.
Inventor(s): Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B41/27, H01L23/528, H10B41/10, H10B41/35
CPC Code(s): H10B41/27
Abstract: in some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. a first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. a barrier structure is arranged between the first and second source/drain conductive lines. a channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. a first dielectric layer is arranged between the barrier structure and the channel layer. a memory layer is arranged on sidewalls of the channel layer. the first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. the first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. the second width is greater than the first width.
Inventor(s): Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-An CHEN of Beitun District (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B41/27, H01L21/033, H01L29/06, H10B43/27
CPC Code(s): H10B41/27
Abstract: in a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. a mask pattern is formed. the mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. the substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. a first field effect transistor (fet) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second fet having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
Inventor(s): Sheng-Chih LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B43/35, G11C5/06, H10B43/10, H10B43/40
CPC Code(s): H10B43/35
Abstract: a method for forming a semiconductor memory device is provided. the method includes forming a stack of alternatingly stacking active layers and insulating layers over an interconnect structure, etching the stack to form a trench, forming a gate structure in the trench, and etching the gate structure to form openings. the gate structure is cut into plurality of gate lines which are physically and electrically isolated from each other.
Inventor(s): Hung-Chang Sun of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Jun Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/00, H01L21/28, H01L29/08
CPC Code(s): H10B51/00
Abstract: a semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. the structure also includes a source structure and a drain structure formed over the channel layer. the structure further includes a first isolation structure formed between the source structure and the drain structure. the source structure extends over the cap layer and towards the drain structure.
Inventor(s): Sai-Hooi Yeong of Cheras (MY) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C5/06, G11C11/22, H01L21/28, H01L29/66, H10B43/10, H10B43/20, H10B51/10, H10B53/20
CPC Code(s): H10B51/20
Abstract: in an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.
Inventor(s): Chao-I Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L21/28, H01L29/51, H10B41/23, H10B51/00, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: provided are a memory device and a method of forming the same. the memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. the layer stack is disposed on the substrate. the layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. the composite pillar structures respectively penetrate through the layer stack. each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.
Inventor(s): Chun-Chieh Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L21/02, H01L29/24, H10B51/30
CPC Code(s): H10B51/20
Abstract: the present disclosure, in some embodiments, relates to an integrated chip structure. the integrated chip structure includes a multi-layer stack disposed on a substrate and having a plurality of conductive layers interleaved between a plurality of dielectric layers. a channel layer is arranged along a side of the multi-layer stack. a ferroelectric material is arranged between the channel layer and the side of the multi-layer stack. a plurality of oxygen scavenging layers are respectively arranged between the ferroelectric material and sidewalls of the plurality of conductive layers. the plurality of oxygen scavenger layers are entirely confined below the plurality of dielectric layers.
Inventor(s): Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C11/22, G11C11/56, H01L21/28, H01L29/66, H01L29/78, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: in an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.
Inventor(s): Chia Yu Ling of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C11/22, H01L29/06, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: in an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.
Inventor(s): Kuen-Yi Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsuan Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Ching Ong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, H10B53/40
CPC Code(s): H10B53/30
Abstract: various embodiments of the present disclosure are directed towards a ferroelectric memory device comprising a chimney seed structure. a ferroelectric layer overlies a bottom electrode layer, and a top electrode layer overlies the ferroelectric layer. the top electrode layer, the ferroelectric layer, and the bottom electrode layer form a plurality of memory cells, and a dielectric wall extends through the top electrode layer and segments the top electrode layer into a plurality top electrodes individual to the memory cells. the chimney seed structure underlies the ferroelectric layer and extends through the bottom electrode layer from the ferroelectric layer. the chimney seed structure is configured to seed ferroelectric crystalline growth in the ferroelectric layer to allow the ferroelectric layer to achieve a large remanent polarization with a small thickness. the small thickness increases read speeds, while the large remanent polarization increases a read window and hence reliability.
Inventor(s): Bi-Shen Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi Yang Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a lower electrode structure disposed over one or more interconnects. the one or more interconnects are arranged within a lower inter-level dielectric (ild) structure over a substrate. a barrier is arranged along a lower surface of the lower electrode structure. the barrier separates the lower electrode structure from the one or more interconnects. an amorphous initiation layer is over the lower electrode structure and a ferroelectric material is on the amorphous initiation layer. the ferroelectric material has a substantially uniform orthorhombic crystalline phase. an upper electrode is over the ferroelectric material.
Inventor(s): Yi Yang WEI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bi-Shen LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang TRINH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Lien LIN of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung KUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. an exemplary ferroelectric stack has a ferroelectric switching layer (fsl) stack disposed between a first electrode and a second electrode. the ferroelectric stack includes a barrier layer disposed between a first fsl and a second fsl, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first fsl and/or the second fsl. in some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. in some embodiments, the first fsl and/or the second fsl include a first metal oxide, and the barrier layer includes a second metal oxide. the ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
Inventor(s): Meng-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, H10B51/20, H10B51/30, H10B53/20
CPC Code(s): H10B53/30
Abstract: a semiconductor device includes a first concentric structure extending along a vertical direction and wrapping around a first conductor structure. the semiconductor device includes a second concentric structure extending along the vertical direction and wrapping around a second conductor structure. the semiconductor device includes a third conductor structure extending along the vertical direction, wherein the third conductor structure is interposed between and spaced from the first and second concentric structures along a first lateral direction. the semiconductor device includes a fourth conductor structure extending along the first lateral direction. the fourth conductor structure at least partially wraps around each of the first concentric structure, the third conductor structure, and the second concentric structure.
Inventor(s): Kuan-Liang Liu of Pingtung City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shiung Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yeong-Jyh Lin of Caotun Township (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H01L21/02, H01L21/285, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H10B61/22
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. the first transistor includes first channel structures extending between first and second source/drain regions. a first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. the second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. a second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. the integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.
Inventor(s): Shy-Jay Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., MingYuan Song of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hiroki Noguchi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H01L29/78, H10N50/01, H10N50/80
CPC Code(s): H10B61/22
Abstract: a method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a spin orbit torque (sot) material on the first electrode and the second electrode, depositing magnetic tunnel junction (mtj) layers on the sot material, depositing a second electrode layer on the mtj layers, etching the sot material to form a sot layer extending from the first electrode to the second electrode, etching the mtj layers to form an mtj stack on the sot layer, and etching the second electrode layer to form a top electrode on the mtj stack.
Inventor(s): Ken-Ichi Goto of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Mauricio Manfrini of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H10B63/00
CPC Code(s): H10B61/22
Abstract: the present disclosure, in some embodiments, relates to a memory device. in some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. a selecting transistor is disposed over the lower interconnect metal layer. a memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cho Wang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jiunyu Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Huang Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H10N50/01, H10N50/10, H10N50/80
CPC Code(s): H10B61/22
Abstract: some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (mram) cell. the integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. the interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. the metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. a bottom electrode is disposed over and in electrical contact with the lower metal layer. a magnetic tunneling junction (mtj) is disposed over an upper surface of bottom electrode. a top electrode is disposed over an upper surface of the mtj. a sidewall spacer surrounds an outer periphery of the top electrode. less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
Inventor(s): Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus VAN DAL of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Timothy VASEN of Tervuren (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10K10/46, H10K10/84, H10K19/10, H10K71/10, H10K71/18, H10K71/20, H10K71/30, H10K71/80, H10K85/20
CPC Code(s): H10K10/484
Abstract: in a method of forming a gate-all-around field effect transistor (gaa fet), a fin structure including cnts embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.
Inventor(s): Guenole Jan of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Jodi Mari Iwata of San Carlos CA (US) for taiwan semiconductor manufacturing company, ltd., Ru-Ying Tong of Los Gatos CA (US) for taiwan semiconductor manufacturing company, ltd., Huanlong Liu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Yuan-Jen Lee of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd., Jian Zhu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, G11C11/16, H01F10/32, H10B61/00, H10N50/10, H10N50/80, H10N50/85
CPC Code(s): H10N50/01
Abstract: a perpendicularly magnetized magnetic tunnel junction (p-mtj) is disclosed wherein a boron containing free layer (fl) is subjected to a plasma treatment with inert gas, and a natural oxidation (nox) process to form bobefore overlying layers are deposited. a metal layer such as mg is deposited on the fl as a first step in forming a hk enhancing layer that increases fl perpendicular magnetic anisotropy, or as a first step in forming a tunnel barrier layer on the fl. one or more anneal steps are essential in assisting bosegregation from the free layer and thereby increasing the fl magnetic moment. a post-oxidation plasma treatment may also be used to partially remove boproximate to the fl top surface before the metal layer is deposited. both plasma treatments use low power (<50 watts) to remove a maximum of 2 angstroms fl thickness.
Inventor(s): Huanlong Liu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Jian Zhu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Keyu Pi of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Ru-Ying Tong of Los Gatos CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, G01R33/09, G11B5/39, G11C11/16, H01F41/30, H10N50/10
CPC Code(s): H10N50/01
Abstract: a method of forming a mtj with a tunnel barrier having a high tunneling magnetoresistance ratio, and low resistance�area value is disclosed. the method preserves perpendicular magnetic anisotropy in bottom and top magnetic layers that adjoin bottom and top surfaces of the tunnel barrier. a key feature is a passive oxidation step of a first mg layer that is deposited on the bottom magnetic layer wherein a maximum oxygen pressure is 10-5 torr. a bottom portion of the first mg layer remains unoxidized thereby protecting the bottom magnetic layer from substantial oxidation during subsequent oxidation and anneal processes that are employed to complete the fabrication of the tunnel barrier and mtj. an uppermost mg layer may be formed as the top layer in the tunnel barrier stack before a top magnetic layer is deposited.
Inventor(s): Nuo Xu of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., Yuan Hao Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Sheng Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang Wu of Chubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01
CPC Code(s): H10N50/80
Abstract: an mram cell block and a magnetic shielding structure for the mram cell block are incorporated into a metal interconnect of an integrated circuit (ic) device. the magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. the magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. the wires and vias may also include a metal that is more conductive than the magnetic shielding material. the metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. the mram cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-d ic device that includes a second substrate having a conventional metal interconnect.
Inventor(s): Joung-Wei Liou of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chin Kun Lan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01
CPC Code(s): H10N50/80
Abstract: an mram cell has a bottom electrode, a metal tunneling junction, and a top electrode. the metal tunneling junction has a side surface between the bottom electrode and the top electrode. a thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. the thin layer has a lower conductance than the mtj. the electrode metal may have been deposited on the side during mtj patterning and subsequently been reacted to from a compound having a lower conductance than a nitride of the electrode metal. the thin layer may include an oxide deposited over the redeposited electrode metal. the thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. a silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.
Inventor(s): Jun-Yao Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cho Wang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/10
CPC Code(s): H10N50/80
Abstract: the present disclosure relate to semiconductor structure that includes a substrate and a memory array. the memory array is spaced over the substrate and has a plurality of rows and a plurality of columns. further, the memory array comprises a first memory cell and a second memory cell that are adjacent at a common elevation above the substrate. the second memory cell is at an edge of the memory array and separates the first memory cell from the edge, and a top surface of the first memory cell is recessed relative to a top surface of the second memory cell.
Inventor(s): Tai-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Feng Yin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An-Shen Chang of Jubei City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting Tsai of Kaoshiung (TW) for taiwan semiconductor manufacturing company, ltd., Qiang Fu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/01
CPC Code(s): H10N50/80
Abstract: in an embodiment, a device includes: a magnetoresistive random access memory (mram) array including mram cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (mtj) stacks over the first bottom electrodes; a first shared electrode over each of the first mtj stacks; second bottom electrodes arranged along the first column; second mtj stacks over the second bottom electrodes; a second shared electrode over each of the second mtj stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.
20240381787. TARGET FOR MRAM_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Wen-Hao Cheng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Chih Chu of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, C23C14/34, H10N50/01
CPC Code(s): H10N50/80
Abstract: a sputtering target structure includes a back plate characterized by a first size and a plurality of sub-targets bonded to the back plate. each of the sub-targets is characterized by a size that is a fraction of the first size and is no greater than a threshold target size. a given sub-target characterized by a size no greater than the threshold target size exhibits no crack formation in a sputtering operation. each of the plurality of sub-targets is in direct contact with one or more adjacent sub targets.
Inventor(s): Chien-Min Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shy-Jay Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Lin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., MingYuan Song of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung Ying Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N52/80, H10B61/00, H10N50/85, H10N52/01
CPC Code(s): H10N52/80
Abstract: semiconductor device includes pair of active devices, composite spin hall electrode, and a magnetic tunnel junction. composite spin hall electrode is electrically connected to pair of active devices. magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. spin hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. pair of heavy metal layers is made of a heavy metal in a metastable state. spacer layer comprises first material different from the pair of heavy metal layers.
Inventor(s): Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10B63/00, H10N70/00
CPC Code(s): H10N70/231
Abstract: memory stacks and method of forming the same are provided. a memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. a width of the top electrode layer is greater than a width of the phase change layer. a first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
Inventor(s): Fa-Shen Jiang of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10B63/00, H10N70/00
CPC Code(s): H10N70/24
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a bottom electrode over a substrate. a top electrode overlies the bottom electrode. a capping structure is disposed between the top electrode and the bottom electrode. the capping structure comprises a diffusion barrier layer vertically stacked with a metal layer. a switching structure is disposed between the bottom electrode and the capping structure. the switching structure comprises a dielectric layer on the bottom electrode and a first oxygen affinity layer on the dielectric layer. a first gibbs free energy of the first oxygen affinity layer is less than a second gibbs free energy of the dielectric layer. a first difference between the first gibbs free energy and the second gibbs free energy is less than −100 kj/mol.
Inventor(s): Mauricio Manfrini of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Gerben Doornbos of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd., Marcus Johannes Henricus van Dal of Linden (BE) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, G11C13/00, H10B63/00
CPC Code(s): H10N70/823
Abstract: some embodiments relate to an integrated chip including a memory device. the memory device includes a bottom electrode disposed over a semiconductor substrate. an upper electrode is disposed over the bottom electrode. an intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. the intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
Inventor(s): Ching Ju Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H10N70/8616
Abstract: the present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. the first memory cell comprises a first data storage layer. a second memory cell is adjacent to the first memory cell. a dielectric layer is disposed laterally between the first memory cell and the second memory cell. an air gap is disposed within the dielectric layer. the air gap is spaced laterally between the first memory cell and the second memory cell.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on November 14th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B01D35/06
- B01D35/30
- B03C1/28
- B03C1/30
- CPC B01D35/06
- Taiwan semiconductor manufacturing company, ltd.
- B06B1/02
- CPC B06B1/0292
- B24B7/22
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- B24B49/12
- CPC B24B7/228
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- CPC B25B11/005
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- CPC B81B3/0021
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- CPC B81B3/0051
- CPC B81C1/00801
- C08L25/14
- C08L33/08
- C08L33/14
- G03F7/004
- G03F7/038
- G03F7/20
- G03F7/40
- CPC C08L25/14
- C23C16/455
- C23C16/458
- H01J37/32
- CPC C23C16/45536
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- H04N23/73
- CPC H04N23/745
- H04R17/00
- H04R7/04
- H04R31/00
- CPC H04R17/00
- G02B7/185
- G02B26/06
- G02B26/08
- G02B27/09
- CPC H05G2/008
- G11C7/12
- G11C11/4096
- G11C11/4097
- CPC H10B10/12
- CPC H10B10/125
- G11C8/08
- G11C8/16
- G11C11/413
- CPC H10B10/18
- H10B51/40
- H01L29/94
- CPC H10B12/33
- H10B41/27
- H10B41/35
- CPC H10B41/27
- H10B43/27
- H10B43/35
- H10B43/40
- CPC H10B43/35
- H10B51/00
- CPC H10B51/00
- H10B51/20
- H10B51/10
- H10B53/20
- CPC H10B51/20
- H10B41/23
- G11C11/56
- H10B53/30
- H10B53/40
- CPC H10B53/30
- H10B61/00
- CPC H10B61/22
- H10N50/80
- H10B63/00
- H10K71/10
- H10K71/18
- H10K71/20
- H10K71/30
- H10K71/80
- CPC H10K10/484
- H01F10/32
- CPC H10N50/01
- G01R33/09
- G11B5/39
- CPC H10N50/80
- C23C14/34
- H10N52/80
- H10N52/01
- CPC H10N52/80
- H10N70/20
- H10N70/00
- CPC H10N70/231
- CPC H10N70/24
- CPC H10N70/823
- CPC H10N70/8616
