Taiwan Semiconductor Manufacturing Company, LTD. patent applications on February 6th, 2025
Patent Applications by Taiwan Semiconductor Manufacturing Company, LTD. on February 6th, 2025
Taiwan Semiconductor Manufacturing Company, LTD.: 66 patent applications
Taiwan Semiconductor Manufacturing Company, LTD. has applied for patents in the areas of H01L29/66 (18), H01L29/423 (13), H01L23/00 (12), H01L29/06 (11), H01L21/768 (10) H10B10/125 (3), H10B20/25 (2), H01L23/535 (2), H01L23/481 (2), H10B51/30 (2)
With keywords such as: layer, semiconductor, structure, substrate, device, dielectric, region, gate, disposed, and electrode in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, LTD.
Inventor(s): Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Wu of Miaoli (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong Ni of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B08B3/02, B08B3/04, H01L21/02, H01L21/67
CPC Code(s): B08B3/02
Abstract: a method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.
Inventor(s): You-Shiun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Chun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Wei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung Lung LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C01F7/54
CPC Code(s): C01F7/54
Abstract: hydrofluoric acid waste streams from semiconductor device manufacturing processes are collected and converted to cryolite utilizing disclosed systems and processes. the systems and processes are able to utilize hydrofluoric acid waste streams from multiple different sources. the systems and processes utilizing control delivery of reactant so that the produced cyrolite has low impurity levels and meets industry standards.
Inventor(s): Chung Hsien Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Mu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Fang Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C16/455, C23C16/52
CPC Code(s): C23C16/45544
Abstract: the thin film deposition system includes: a deposition chamber, a precursor source container containing a precursor source; and a precursor conduit. the precursor conduit is elongated and extends between a proximate end and a distal end, and the proximate end is coupled to an outlet of the precursor source container, and the distal end is coupled to an inlet of the deposition chamber.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/136, G02B6/124, H01L23/00, H01L25/16, H01L25/18
CPC Code(s): G02B6/136
Abstract: a method includes forming an optical interposer, comprising: forming an optical device layer over a front-side of a first substrate, the optical device layer comprising a grating coupler; forming a first interconnect structure over the optical device layer, the first interconnect structure comprising conductive features and dielectric layers; etching an opening through the dielectric layers to expose the grating coupler; filling the opening with an oxide layer; forming a first bond layer over a back-side of the first substrate, the first bond layer comprising first bond pads and a first dielectric bond layer; and attaching a semiconductor device to the optical interposer, the semiconductor device comprising: an active device layer over a front-side of a second substrate; a second interconnect structure over the active device layer; and a second bond layer over the second interconnect structure, the second bond layer comprising second bond pads and a second dielectric bond layer.
Inventor(s): Chao-Jen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Fu Tsai of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/30, G02B6/32
CPC Code(s): G02B6/30
Abstract: a package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a first end of the second waveguide is optically coupled to the first waveguide, wherein the waveguide structure is configured to be connected to an optical fiber component such that a second end of the second waveguide is optically coupled to an optical fiber of the optical fiber component.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Tsung Tsai of Tainan City (CN) for taiwan semiconductor manufacturing company, ltd., Kuo Chin Hsu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4214
Abstract: optical devices and methods of manufacture are presented in which a mirror structure is utilized with an optical interposer. in embodiments a method patterns a substrate to form a recess with a sidewall, forms a mirror coating on the sidewall, deposits and patterns a material to form a first waveguide adjacent to the mirror coating, and bonds an optical interposer over the first waveguide.
Inventor(s): Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Huang of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/423
Abstract: a package includes an optical engine attached to a package substrate, wherein the optical engine includes a first waveguide; and a waveguide structure attached to the package substrate adjacent the optical engine, wherein the waveguide structure includes a second waveguide within a transparent block, wherein a bottom surface of the transparent block is nonplanar, wherein the second waveguide is a fixed distance from the bottom surface along its length, wherein the second waveguide is optically coupled to the first waveguide.
Inventor(s): Ru-Gun LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyu-Horng SHIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Yin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Huei SUEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya Hui CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Nien SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sung YEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fong CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Wen YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Tien SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F1/22, G03F1/36, G03F1/70, G03F7/40, H01L21/027
CPC Code(s): G03F7/70558
Abstract: in a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
Inventor(s): Szu-Chun Tsao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jaw-Juinn Horng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bindu Madhavi Kasina of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Wen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F1/46, G05F3/26, G05F3/30
CPC Code(s): G05F1/468
Abstract: systems and methods as described herein may take a variety of forms. in one example, systems and methods are provided for a circuit for powering a voltage regulator. a voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. a power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.
Inventor(s): Sandeep Goel of Dublin CA (US) for taiwan semiconductor manufacturing company, ltd., Ankita Patidar of San Jose CA (US) for taiwan semiconductor manufacturing company, ltd., YUN-HAN LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/08
CPC Code(s): G06F1/08
Abstract: a semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. the on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.
Inventor(s): Kao-Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min Chan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yuan Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chen Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang Lin Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419
CPC Code(s): G11C11/419
Abstract: a memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. the first voltage drop is substantially smaller than the second voltage drop.
Inventor(s): Ying-Chieh Meng of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/08
CPC Code(s): H01J37/08
Abstract: an ion generator of an ion implanter is provided. the ion generator includes: an arc chamber defined by an arc chamber housing extending in a traveling direction; a filament configured to generate thermal electrons; a cathode disposed at a first end of the arc chamber housing in the traveling direction and configured to generate secondary electrons in response to bombardment of the thermal electrons generated by the filament; and a repeller disposed at a second end, opposite to the first end, of the arc chamber housing in the traveling direction, wherein the repeller is movable with respect to the arc chamber housing.
Inventor(s): Chih-Lun LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Wei PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Teng LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, B01D46/42, C23C16/44, C23C16/50, H05B1/02
CPC Code(s): H01J37/32844
Abstract: an apparatus includes a process chamber, a vacuum pump disposed downstream of the process chamber for discharging a fluid flow from the process chamber, a filter mounted between the process chamber and the vacuum pump for filtering the fluid flow, and a heating device disposed to heat the filter.
Inventor(s): Chung Hsien Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po Wen Yang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Mu Cho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Fang Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67248
Abstract: a semiconductor processing system is provided. the semiconductor processing system includes a first chamber arranged to perform a first semiconductor process; a second chamber arranged to perform a second semiconductor process; a cooling chamber having a pedestal; and a plurality of non-contact temperature sensors mounted in the cooling chamber, and arranged to measure a temperature of a wafer disposed on the pedestal. in one aspect, the first chamber is arranged to transfer the wafer to the cooling chamber upon completion of the first semiconductor process in the first chamber. in another aspect, the cooling chamber is arranged to measure the temperature of the wafer in the cooling chamber and arranged to transfer the wafer to the second chamber when the temperature of wafer is at a target temperature, or pause processing of the wafer when the temperature of the wafer is not at the target temperature.
Inventor(s): Tsung-Chieh Hsiao of Shetou Township (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Pin Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Feng Chen of Yilan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/00, H01L25/065
CPC Code(s): H01L23/367
Abstract: a method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. a cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.
Inventor(s): Shao-Kuan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw Tsai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin Teng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Fang Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L21/768, H01L23/48, H01L23/532
CPC Code(s): H01L23/373
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. the electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. the thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. further, the thermal interconnect structure is embedded within the interconnect dielectric layers. the thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. the thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Gang Wen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L23/367, H01L23/498, H01L23/528, H01L25/065
CPC Code(s): H01L23/481
Abstract: a method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. the first trenches extend partially into the carrier substrate for a distance less than the second trenches. the method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. the first conductive features remain partially embedded in the carrier substrate.
Inventor(s): Chien-Hsun Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/762, H01L21/768, H01L23/522
CPC Code(s): H01L23/481
Abstract: in an embodiment, a method includes: forming a first opening in a semiconductor substrate, in a plan view the first opening having a ring shape; forming a dielectric guard ring in the first opening; forming an active device along a first surface of the semiconductor substrate; forming first metallization layers over the active device; forming a second opening through the semiconductor substrate, the second opening adjacent to the ring shape of the dielectric guard ring; forming a conductive through via in the second opening; and forming second metallization layers over the first metallization layers.
Inventor(s): Chih-Chao Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen Chang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L25/065
CPC Code(s): H01L23/49838
Abstract: a method includes forming a first device die and a second device die. the first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. the first integrated circuit is electrically connected to the first bond pad. the second device die includes a power switch that includes a first source/drain region, a second source/drain region, a second bond pad electrically connecting to the first source/drain region, and a third bond pad electrically connecting to the second source/drain region. the method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.
Inventor(s): Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/768, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/535
Abstract: embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. a semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. the backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.
Inventor(s): Jung-Chan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/535, H01L21/768, H01L21/8234, H01L23/522, H01L23/528, H01L23/538, H01L27/02, H01L29/40, H01L29/417
CPC Code(s): H01L23/535
Abstract: a method of forming a semiconductor device includes forming first, second and third metal-to-drain/source (md) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to a doped region. the method further includes forming a via-to-via (v2v) rail which extends in a second direction angled with respect to the first direction, wherein the v2v rail overlaps at least of the first md contact structure or the third md contact structure. the method further includes forming a first via-to-md (vd) structure over, and electrically coupled to, the first md contact structure and the v2v rail. the method further includes forming a first conductive segment which overlaps the v2v rail, is in a first metallization layer, and is electrically coupled to the first vd structure.
Inventor(s): Hsien-Wei CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/498
CPC Code(s): H01L23/5383
Abstract: a semiconductor package, which may correspond to a high-performance computing package, includes an integrated circuit die electrically and/or mechanically connected to a top surface of an interposer and a plurality of connection structures electrically and/or mechanically connected to a bottom surface of the interposer. the top surface of the interposer includes a set of test contact structures (e.g., one or more test bumps) that are electrically connected to the integrated circuit die through traces of the interposer. the set of test structures may be contacted by a probe needle to test a quality and/or a reliability of the integrated circuit die, as well as verify that traces of the interposer are functional. the set of test contact structures allows the integrated circuit die and traces of the interposer to be tested without probing the connection structures.
Inventor(s): Wei-Hung Lin of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chun Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hua Lo of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chih Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Hsien Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/564
Abstract: a package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. a diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.
Inventor(s): Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L27/02, H01L27/06
CPC Code(s): H01L23/576
Abstract: some embodiments relate to an integrated device including a first thin film transistor (tft) arranged over a substrate; a second tft arranged over the substrate; a metal barrier layer arranged over the second tft, where the metal barrier layer is configured to block incident radiation from reaching the second tft; a fresnel lens arranged over the first tft, where the fresnel lens is configured to focus incident radiation towards the first tft; and where the first tft and the second tft are configured to be coupled to a differential amplifier, the differential amplifier being operable to detect the incident radiation by comparison of a first leakage current from the first tft to a second leakage current from the second tft.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Li Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/522, H01L23/64
CPC Code(s): H01L24/05
Abstract: provided is packages and method of fabricating the same. the package includes a first die, a second die, and an inductor. the second die is bonded to the first die through a bonding structure thereof. the inductor is located in the bonding structure. the inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.
Inventor(s): Chin-Hao HSU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Anhao CHENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Shang HSIAO of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/522
CPC Code(s): H01L24/08
Abstract: a metal layer of a semiconductor device may be included in an extreme low dielectric constant (elk) dielectric layer in an interconnect structure of the semiconductor device. the metal layer may be coupled with a bonding via that extends through a silicon carbide (sic) layer in a bonding region of the semiconductor device. the elk dielectric layer and/or the silicon carbide layer reduces stress migration in the semiconductor relative to the use of other dielectric materials such as silicon nitride and/or silicon glass. the elk dielectric layer and/or the silicon carbide layer also reduces resistance-capacitance (rc) delay in the interconnect structure relative to the use of other dielectric materials. the elk dielectric layer and/or the silicon carbide layer provides improved adhesion with the metal material(s) (e.g., copper and/or another metal material) of the metal layer and/or of the bonding via coupled with the metal layer.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L25/00, H01L25/065, H01L25/16
CPC Code(s): H01L24/29
Abstract: a semiconductor device comprising a first semiconductor component and a composite bonding layer on the first semiconductor component. the composite bonding layer comprises a dielectric stress buffer layer and a dielectric planarization layer, wherein a hardness of the dielectric stress buffer layer is greater than a hardness of the dielectric planarization layer. the semiconductor device further includes a second semiconductor component bonded to the first semiconductor component by insulator-to-insulator bonding between the composite bonding layer and an insulating bonding layer on the second semiconductor component, wherein the dielectric planarization layer is disposed an interface between the composite bonding layer and the insulating bonding layer.
Inventor(s): Chih-Wei Wu of Zhuangwei Township (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L25/00
CPC Code(s): H01L25/0652
Abstract: a method of manufacturing a semiconductor device, the method includes bonding a first die and a second die to a first side of a wafer, wherein after bonding the first die and the second die to the first side of the wafer, a gap is disposed between the first die and the second die, wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap, depositing a third dielectric layer on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap, forming a molding material over the third dielectric layer to fill the gap, and performing a planarization process to expose top surfaces of the first die and the second die.
Inventor(s): Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yi Ling Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/58
CPC Code(s): H01L25/0657
Abstract: interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. an exemplary system on integrated circuit (soic) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. a through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. the backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. the through via may be connected to a redistribution layer (rdl) structure.
Inventor(s): Yu-Hsun Li of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02N1/00
CPC Code(s): H02N1/008
Abstract: mems actuators having micro spring structures and methods of fabricating the same are provided. an example mems actuator includes a first micromechanical arm array including multiple first micromechanical arms spaced from each other in a first horizontal direction and a second micromechanical arm array including multiple second micromechanical arms spaced from each other in the first horizontal direction. the first and the second micromechanical arm arrays are interposed in the first horizontal direction. the mems actuator further includes a metal connection structure connected to each first micromechanical arm, and a vertical micro spring structure disposed between the metal connection structure and one of the second micromechanical arms. the vertical micro spring structure includes an upper portion connected to the metal connection structure and a lower portion connected to a top end of the second micromechanical arm.
Inventor(s): Zhen TANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lei PAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Miranda MA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/16, H03K5/12, H03K17/14, H03K17/687
CPC Code(s): H03K17/166
Abstract: in a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned on to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned off and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. the second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. the second changing rate is controlled by a passive circuit and is smaller than the first changing rate.
Inventor(s): Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412
CPC Code(s): H10B10/12
Abstract: an integrated circuit structure is provided. the integrated circuit structure includes at least one static random-access memory (sram) cell. the sram cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. the first active region and the second active region follow a first routing direction. the first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. the first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. each of the at least one sram cell has a y-pitch along the first routing direction. the y-pitch is 4x contacted poly pitch.
Inventor(s): Yen Yu Chen of Pingtung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yen Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsing Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Han Chiou of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/8238, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10B10/125
Abstract: a method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. the dielectric structure divides the metal gate into two sections.
Inventor(s): Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ching Wang of Kinmen County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L23/522, H01L23/528
CPC Code(s): H10B10/125
Abstract: an integrated circuit (ic) device has a memory region in which a plurality of memory cells is implemented. each of the memory cells has a first dimension in a first horizontal direction. the ic device includes an edge region bordering the memory cell region in the first horizontal direction. the edge region has a second dimension in the first horizontal direction. the second dimension is less than or equal to about 4 times the first dimension. the ic device is formed by revising a first ic layout to generate a second ic layout. the second ic layout is generated by shrinking a dimension of the edge region in the first horizontal direction.
Inventor(s): Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Bey Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: the present disclosure provides an ic structure that includes a semiconductor substrate having a sram region, an input/output and peripheral (iop) region, and an edge region spanning tween the sram region and the iop region; a sti structure formed on the semiconductor substrate and defining active regions; a sram cell formed within the sram region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the sti structure. the active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch p along the first direction; the sram cell spans a first dimension ds along the first direction; the edge region spans a second dimension de along the first direction; and a ratio de/ds equals to 2 or is less than 2.
Inventor(s): Yu-Wei Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/25
CPC Code(s): H10B20/25
Abstract: a memory device includes a plurality of one-time-programming (otp) memory cells grouped at least into a first portion and a second portion, wherein the first and second portions are disposed next to each other along a first lateral direction; a first driver circuit disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion and the first driver circuit along the first lateral direction; and a second driver circuit disposed next to both of the first and second portions along a second lateral direction perpendicular to the first lateral direction. the otp memory cells of the first portion are associated with a first electrical/physical characteristic and the otp memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.
Inventor(s): Jui-Lin Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Sheng Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/25, H01L23/525
CPC Code(s): H10B20/25
Abstract: the present disclosure provides embodiments of electronic fuse devices. an electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. the first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.
Inventor(s): Shih-Yu LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, G11C11/22, H01L23/528, H01L29/66, H01L29/78, H10B51/10
CPC Code(s): H10B51/30
Abstract: the present disclosure describes a structure with a substrate, a first interconnect region, a second interconnect region, and a memory device region. the first interconnect region is over the substrate and includes first interconnect structures. the second interconnect region is over the first interconnect region and includes second interconnect structures electrically connected to the first interconnect structures. further, the memory device region is between the first and second interconnect regions and includes memory cells (e.g., ferroelectric random access memory (feram) cells).
Inventor(s): Bi-Shen Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yu Lin of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Yang Wei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yuan Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/30, H10B53/30
CPC Code(s): H10B51/30
Abstract: in some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. the first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
Inventor(s): Chih-Hsiang Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chi Tu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Yu Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Chen Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B53/30, G11C11/22, H01L21/28, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H10B53/30
Abstract: in some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
Inventor(s): Meng-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih Weng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Hua Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H01L21/768, H01L23/522, H01L27/08
CPC Code(s): H01L28/91
Abstract: in some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
Inventor(s): Chi-Yuan Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Fung Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., Yan-Jie Liao of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/30
CPC Code(s): H01L28/75
Abstract: in some embodiments, the present disclosure relates to an integrated chip structure that includes a metal-insulator-metal (mim) device disposed over a substrate. the mim device includes a first electrode and a second electrode stacked over the substrate. a dielectric layer is arranged between the first electrode and the second electrode. a getter layer is disposed over the substrate and is separated from the dielectric layer by the first electrode. the mim device includes a middle portion having a first non-zero concentration of hydrogen and a peripheral portion having both a second non-zero concentration of hydrogen that is greater than the first non-zero concentration and a third non-zero concentration of hydrogen that is less than the first non-zero concentration. the middle portion includes the dielectric layer and the peripheral portion includes the getter layer.
Inventor(s): Pin-Chu LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Chang SUNG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng LI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L21/311, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a method for manufacturing a semiconductor device is provided. the method includes forming an epitaxial stack over a substrate, the epitaxial stack comprising alternating sacrificial layers and channel layers; patterning the epitaxial stack into a first fin and a second fin; forming a dielectric wall between the first and second fins; forming a dielectric structure surrounding the first and second fins; depositing a protection layer over the first and second fins; after depositing the protection layer, etching back the dielectric structure to exposes sidewalls of the sacrificial layers; and replacing the sacrificial layers with a gate structure.
Inventor(s): Chih-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shuo HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Yung LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/8234, H01L21/8238, H01L21/84, H01L27/04, H01L27/088, H01L27/12, H01L29/78, H01L29/786, H10K50/805
CPC Code(s): H01L29/4908
Abstract: a semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. fin structure's lower portion is embedded in first insulating layer. first gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. the first and second gate electrode structures are spaced apart and extend along line in same direction. first and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. each of first and second insulating sidewall spacers contiguously extend along second direction. a second insulating layer is in region between first and second gate electrode structures. the second insulating layer separates first and second gate electrode structures. a third insulating layer is in region between first and second gate electrode structures. the third insulating layer is formed of different material than second insulating layer.
Inventor(s): Chih-Yu Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mauricio Manfrini of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung Wei Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/24, H01L29/51, H01L29/66
CPC Code(s): H01L29/78391
Abstract: the present disclosure relates a device. the device includes a ferroelectric structure having a first side and a second side. a gate structure is disposed along the first side of the ferroelectric structure. an oxide semiconductor is disposed along the second side of the ferroelectric structure and has a first semiconductor conductivity type. a source and a drain are disposed on the oxide semiconductor. a semiconductor layer is arranged on the oxide semiconductor between sidewalls of the source and the drain. the semiconductor layer includes a semiconductor material having a second semiconductor conductivity type that is different than the first semiconductor conductivity type. the semiconductor layer includes p-doped silicon, p-doped germanium, n-doped silicon, or n-doped germanium.
Inventor(s): Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Gu-Huan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Lin Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L23/522, H01L23/528, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786, H10B20/25
CPC Code(s): H01L29/0649
Abstract: the present disclosure provides an integrated circuit (ic) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (sti) structure formed in the semiconductor substrate and defining an active region, wherein the sti structure includes a sti bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the sti bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (fet) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the sti bottom surface.
Inventor(s): Ji-Yin Tsai of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Zheng Hui Lim of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jet-Rung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun Ma of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Horng Li of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/423, H01L29/66
CPC Code(s): H01L29/0673
Abstract: methods of forming a stacked transistor are provided. one representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. the semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. the first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. the representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. the etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. the representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.
Inventor(s): Cheng-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lin FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Hsiung CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xiangdong CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L23/522, H01L29/40, H01L29/423
CPC Code(s): H01L29/0696
Abstract: a method of manufacturing a semiconductor device includes forming first and second active regions; forming first to fifth gate electrodes, the second gate electrode being between the first and third gate electrodes, the fourth gate electrode being between the third and fifth gate electrodes; and selectively replacing at least one portion of at least one of the gate electrodes with an isolation dummy gate, including: replacing the first and fifth gate electrodes with first and second isolation dummy gates formed in trenches through the first and second active regions; and replacing a first portion of the third gate electrode overlying the second active region with a third isolation dummy gate formed in a first trench through the second active region, resulting in a second portion of the third gate over the first active region, and the third isolation dummy gate aligned with the second portion of the third gate.
Inventor(s): Chung-Hsien YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu MA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Syun WONG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/0847
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a source/drain epitaxial feature disposed over a substrate, and the source/drain epitaxial feature includes about 0.002 atomic percent to about 0.02 atomic percent of aluminum. the structure further includes a first semiconductor layer in contact with the source/drain epitaxial feature and a gate electrode layer disposed over the first semiconductor layer.
Inventor(s): Cheng-Yu Wei of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Ming Tang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Han Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L21/8238, H01L21/8258, H01L27/092, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/6653
Abstract: semiconductor devices and methods of manufacture are presented. in embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.
Inventor(s): Hong-Chih CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ting YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66545
Abstract: a semiconductor device includes a semiconductor substrate, a plurality of metal portions, a plurality of nanosheet structures, and a plurality of isolation structures. the metal portions are disposed on the semiconductor substrate and are spaced apart from each other. the nanosheet structures are surrounded by the metal portions such that the nanosheet structures are spaced apart from each other. the isolation structures are disposed on the semiconductor substrate such that two adjacent ones of the metal portions are isolated from each other by a corresponding one of the isolation structures. each of the isolation structures includes a first dielectric layer and an air gap surrounded by the first dielectric layer.
Inventor(s): Tsung-Jui WU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yin HSU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ying Ming WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hsin YANG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H01L29/6656
Abstract: a sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. the sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. the sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. the sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.
Inventor(s): Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/762, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/4175
Abstract: an integrated circuit includes a substrate having a semiconductor layer. the integrated circuit includes a transistor. the transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. a backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. a frontside source/drain contact is directly above and electrically coupled to the first source/drain region. a bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.
Inventor(s): Chung-Ting KO of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Shu Ling LIAO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Sung-En LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41775
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a source/drain (s/d) feature disposed in a recess between two adjacent channel regions, wherein the s/d feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. the structure also includes a silicide layer conformally disposed on the s/d feature, and a s/d contact disposed on the silicide layer, wherein the s/d contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the s/d feature.
Inventor(s): Hung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/82, H01L21/683, H01L21/762, H01L21/768
CPC Code(s): H01L21/8213
Abstract: semiconductor wafers and methods of fabricating the same are provided. an example semiconductor wafer has multiple die regions separated by a die spacing region and includes a wafer substrate, multiple dies disposed over the wafer substrate, and multiple buried sacrificial structures corresponding to the multiple dies. each die is located in the corresponding die region and further includes a die substrate, an integrated circuit (ic) device disposed in the die substrate, and a multi-layer interconnect structure disposed on the ic device. the buried sacrificial structure is surrounding the die substrate and disposed between the die and the wafer substrate. the buried sacrificial structure further includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. the side portion is located in the die spacing region surrounding the corresponding die and disposed on the sidewall of the die substrate.
Inventor(s): Yen Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Yin Tsai of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Jet-Rung Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zheng Hui Lim of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun Ma of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L29/66
CPC Code(s): H01L21/823878
Abstract: embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. the substrate is used to form a field effect transistor fet structure. after formation of the fet, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. the sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.
Inventor(s): Chandrashekhar Prakash SAVANT of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Wei Yu of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ming Tsai of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L21/823431
Abstract: the present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping and to form multiple devices with different v. the method includes forming a gate dielectric layer on a fin structure, forming a buffer layer on the gate dielectric layer, and forming a dopant source layer including a dopant on the buffer layer. the gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. the method further includes doping a portion of the high-k dielectric layer adjacent to the interfacial layer with the dopant, removing the dopant source layer and the buffer layer, forming a dopant pulling layer on the gate dielectric layer, and tuning the dopant in the gate dielectric layer by the dopant pulling layer.
Inventor(s): Cheng-I LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Han CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L27/092
Abstract: a semiconductor device structure and methods of forming the same are described. the structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. the structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Hung Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chunyao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: a semiconductor device and method of manufacture are provided. in embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. the dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.
Inventor(s): Katherine H. Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L29/786, H10B99/00
CPC Code(s): H01L27/124
Abstract: a memory device includes a plurality of memory cells. a first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. a first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. the first read source is coupled to the first write source. a first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.
Inventor(s): Yung-Chang Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsien Hsieh of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-I Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14643
Abstract: the present disclosure relates to an integrated chip. the integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. a second semiconductor material is disposed on the substrate. a doped region is between the substrate and a part of the second semiconductor material. the second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. the projection extends through the doped region.
Inventor(s): Hsiang-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Shin Chu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Kai Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Jiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L31/105
CPC Code(s): H01L27/14623
Abstract: various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. a device layer overlies a substrate. further, a cap layer overlies the device layer. the cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. for example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. a photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. the passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
Inventor(s): Wen-Shun LO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng Kai YEH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Hwang YANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yuan SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Fen HUANG of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L31/024, G02B6/122, H01L21/768
CPC Code(s): H01L31/024
Abstract: a modulator heater structure may include a plurality of regions having different thicknesses. for example, a heater ring of the modulator heater structure may have a first thickness. a heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. the lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. the greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.
Inventor(s): Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Carlos H. Diaz of Los Altos Hills CA (US) for taiwan semiconductor manufacturing company, ltd., Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H01L23/528, H10B41/10, H10B61/00, H10B63/00, H10B63/10, H10N70/00
CPC Code(s): H10N70/231
Abstract: provided are a memory cell and a method of forming the same. the memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. the etching stop layer is disposed on the bottom electrode. the variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. the top electrode is disposed on the variable resistance layer. a semiconductor device having the memory cell is also provided.
Inventor(s): Chao-I Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H10N70/826
Abstract: memory devices and methods of forming the same are provided. a memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. the first conductive layer is disposed over the substrate. the phase change layer is disposed over the first conductive layer. the selector layer is disposed between the phase change layer and the first conductive layer. the second conductive layer is disposed over the phase change layer. in some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.
20250048943. MEMORY STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chieh-Fei Chiu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Shiuan Tsair of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wen Liao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Yu Mei of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Tseng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H01L23/31, H01L23/48, H01L23/495
CPC Code(s): H10N70/8265
Abstract: the present disclosure, in some embodiments, relates to an integrated chip. the integrated chip includes a memory device arranged over an etch stop material on a substrate. the memory device includes a data storage structure disposed between a bottom electrode and a top electrode. a first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. an insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. the bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.
Taiwan Semiconductor Manufacturing Company, LTD. patent applications on February 6th, 2025
- Taiwan Semiconductor Manufacturing Company, LTD.
- B08B3/02
- B08B3/04
- H01L21/02
- H01L21/67
- CPC B08B3/02
- Taiwan semiconductor manufacturing company, ltd.
- C01F7/54
- CPC C01F7/54
- C23C16/455
- C23C16/52
- CPC C23C16/45544
- G02B6/136
- G02B6/124
- H01L23/00
- H01L25/16
- H01L25/18
- CPC G02B6/136
- G02B6/30
- G02B6/32
- CPC G02B6/30
- G02B6/42
- CPC G02B6/4214
- CPC G02B6/423
- G03F7/00
- G03F1/22
- G03F1/36
- G03F1/70
- G03F7/40
- H01L21/027
- CPC G03F7/70558
- G05F1/46
- G05F3/26
- G05F3/30
- CPC G05F1/468
- G06F1/08
- CPC G06F1/08
- G11C11/419
- CPC G11C11/419
- H01J37/08
- CPC H01J37/08
- H01J37/32
- B01D46/42
- C23C16/44
- C23C16/50
- H05B1/02
- CPC H01J37/32844
- CPC H01L21/67248
- H01L23/367
- H01L25/065
- CPC H01L23/367
- H01L23/373
- H01L21/768
- H01L23/48
- H01L23/532
- CPC H01L23/373
- H01L23/498
- H01L23/528
- CPC H01L23/481
- H01L21/762
- H01L23/522
- CPC H01L23/49838
- H01L23/535
- H01L29/06
- H01L29/40
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/775
- CPC H01L23/535
- H01L21/8234
- H01L23/538
- H01L27/02
- CPC H01L23/5383
- CPC H01L23/564
- H01L27/06
- CPC H01L23/576
- H01L23/64
- CPC H01L24/05
- CPC H01L24/08
- H01L21/48
- H01L25/00
- CPC H01L24/29
- H01L21/56
- H01L21/78
- H01L23/31
- CPC H01L25/0652
- H01L23/58
- CPC H01L25/0657
- H02N1/00
- CPC H02N1/008
- H03K17/16
- H03K5/12
- H03K17/14
- H03K17/687
- CPC H03K17/166
- H10B10/00
- G11C11/412
- CPC H10B10/12
- H01L21/8238
- H01L29/78
- CPC H10B10/125
- H10B20/25
- CPC H10B20/25
- H01L23/525
- H10B51/30
- G11C11/22
- H10B51/10
- CPC H10B51/30
- H10B53/30
- H01L21/28
- H01L29/51
- CPC H10B53/30
- H10N70/00
- H01L27/08
- CPC H01L28/91
- H01G4/30
- CPC H01L28/75
- H01L21/311
- H01L27/088
- CPC H01L29/775
- H01L29/49
- H01L21/84
- H01L27/04
- H01L27/12
- H01L29/786
- H10K50/805
- CPC H01L29/4908
- H01L29/24
- CPC H01L29/78391
- H01L27/092
- CPC H01L29/0649
- CPC H01L29/0673
- CPC H01L29/0696
- H01L29/08
- CPC H01L29/0847
- H01L21/8258
- CPC H01L29/6653
- CPC H01L29/66545
- CPC H01L29/6656
- CPC H01L29/4175
- CPC H01L29/41775
- H01L21/82
- H01L21/683
- CPC H01L21/8213
- CPC H01L21/823878
- CPC H01L21/823431
- CPC H01L27/092
- CPC H01L27/0924
- H10B99/00
- CPC H01L27/124
- H01L27/146
- CPC H01L27/14643
- H01L31/105
- CPC H01L27/14623
- H01L31/024
- G02B6/122
- CPC H01L31/024
- H10N70/20
- H10B41/10
- H10B61/00
- H10B63/00
- H10B63/10
- CPC H10N70/231
- CPC H10N70/826
- H01L23/495
- CPC H10N70/8265