Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on June 13th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on June 13th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 59 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (19), H01L29/423 (16), H01L29/78 (13), H01L23/522 (12), H01L29/06 (12) H01L27/0886 (3), H01L29/42392 (2), G03F1/24 (2), H01L23/5226 (2), H01L23/481 (2)
With keywords such as: layer, structure, semiconductor, gate, dielectric, substrate, region, die, device, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Tsung-Sheng KUO of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Hsu-Shui LIU of Pingjhen City, Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yang-Ann CHU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chieh-Chun LIN of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Shine CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B65B5/04, B65G47/28, G01N21/95, G06T7/00
CPC Code(s): B65B5/045
Abstract: in certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
Inventor(s): Chien-Wei CHANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Ya-Jen SHEUH of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Ren-Dou LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chih CHANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun CHIU of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Hsin CHI of Taichung County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B81C1/00, H01L21/02, H01L21/3105, H01L21/66
CPC Code(s): B81C1/00238
Abstract: methods for improving wafer bonding performance are disclosed herein. in some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. the method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (cvd), and performing at least one chemical mechanical polishing (cmp). one of the at least one cvd is performed after all cmp performed before bonding.
Inventor(s): Chung-Ming Weng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Yi Kuo of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Yuan Yu of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Hua-Kuei Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Che-Hsiang Hsu of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/43, G02B6/42
CPC Code(s): G02B6/43
Abstract: a package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
Inventor(s): Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Cheng LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: an extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. the patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. the at least one alloying element includes at least one transition metal element or at least one group 14 element.
Inventor(s): Yun-Yue LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/24
CPC Code(s): G03F1/24
Abstract: a photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. the capping layer includes a non-crystalline conductive material.
Inventor(s): Chih-Tsung SHIH of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Chih CHIEN of Caotun Township (TW) for taiwan semiconductor manufacturing co., ltd., Tsung Chuan LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Shiang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/66, G03F7/00, H01L21/027, H01L21/673
CPC Code(s): G03F1/66
Abstract: a reticle enclosure includes a base including a first surface, a cover including a second surface and coupled to the base with the first surface facing the second surface. the base and the cover form an internal space that includes a reticle. the reticle enclosure includes restraining mechanisms arranged in the internal space and for securing the reticle, and structures disposed adjacent the reticle in the internal space. the structures enclose the reticle at least partially, and limit passage of contaminants between the internal space and an external environment of the reticle enclosure. the structures include barriers disposed on the first and second surfaces. in other examples, a padding is installed in gaps between the barriers and the first and second surfaces. in other examples, the structures include wall structures disposed on the first and second surfaces and between the restraining mechanisms.
Inventor(s): Tzu-Yang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/11, G03F7/09, H01L21/027
CPC Code(s): G03F7/11
Abstract: a patterning stack is provided. the patterning stack includes a bottom anti-reflective coating (barc) layer over a substrate, a photoresist layer having a first etching resistance over the barc layer, and a top coating layer having a second etching resistance greater than the first etching resistance over the photoresist layer. the top coating layer includes a polymer having a polymer backbone including at least one functional unit of high etching resistance and one or more acid labile groups attacked to the polymer backbone or a silicon cage compound.
Inventor(s): Jui-Cheng HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsing HSIAO of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jie HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Tsun CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Allen Timothy CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F1/20, G06F1/04
CPC Code(s): G06F1/206
Abstract: in an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
20240192882.MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jun-Shen WU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-En WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ren-Shuo LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a memory device is provided, including a memory array and a selection circuit. at least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. the selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. the selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
Inventor(s): Jaw-Juinn HORNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Shen CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G06F30/392
CPC Code(s): G06F30/398
Abstract: a semiconductor device includes an edge active cell, an inner active cell and a middle active cell. the edge active cell is located near an edge of the semiconductor device. the edge active cell includes a plurality of fingers. the inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. the inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. the middle active cell is located near the central portion of the semiconductor device. the middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C8/08, G11C29/02, G11C29/12, G11C29/50, H01L21/822
CPC Code(s): G11C8/08
Abstract: a test structure for 3d memory arrays and methods of forming the same are disclosed. in an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (os) layer contacting a first source line and a first bit line, the memory film being between the os layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.
Inventor(s): Elia Ambrosi of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Min Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/003
Abstract: first fire operations for an ovonic threshold switch (ots) selector is provided. a first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the ots selector; sensing an output current passing through the ots selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the ots selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the ots selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
Inventor(s): Yi-Ruei JHAN of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Yu LIN of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, H01L21/265, H01L21/3105, H01L29/40, H01L29/66
CPC Code(s): H01L21/02321
Abstract: a method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. the second dosage source is different from the first dosage source.
Inventor(s): Chung-Liang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/48, C25D3/38, C25D7/12, H01L21/56
CPC Code(s): H01L21/486
Abstract: a method including the following steps is provided. a seed layer is formed. conductive material is formed on the seed layer by performing an electrolytic plating process with an electrolytic composition comprising: a source of copper ions; an accelerator agent; and a suppressor agent, by structure represented (1) or (2):
Inventor(s): Chung-Liang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/48, C25D3/38, C25D7/12, H01L21/56
CPC Code(s): H01L21/486
Abstract:
Inventor(s): Chung-Liang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Che Ho of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/48, C25D3/38, C25D7/12, H01L21/56
CPC Code(s): H01L21/486
Abstract: wherein x is between 2 and 50, y is between 5 and 75, and r1 is an alkyl group of 1 to 3 carbon atoms. a portion of the seed layer exposed by the conductive material is removed.
Inventor(s): Kai-An CHUANG of Miaoli (TW) for taiwan semiconductor manufacturing co., ltd., Kuang-Wei HSUEH of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Huan CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Shu KAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/68, G01B7/31
CPC Code(s): H01L21/681
Abstract: an optical system may include a light source to provide a beam of light. the optical system may include a reflector to receive and redirect the beam of light. the optical system may include a light gate having an opening to permit the beam of light, from the reflector, to travel through the opening. the optical system may include a light sensor to receive a portion of the beam of light after the beam of light travels through the opening, and convert the portion of the beam of light to a signal. the optical system may include a processing device to determine whether a notch of a wafer is in an allowable position based on the signal.
Inventor(s): Chao-Hsun WANG of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Wang-Jung HSUEH of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Yi CHAO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/3105, H01L21/321, H01L21/8234, H01L29/08, H01L29/417, H01L29/423, H01L29/49
CPC Code(s): H01L21/76807
Abstract: a method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. an opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. a second dielectric layer is deposited over the first dielectric layer and over the first metal layer. the first and second dielectric layers are etched to form a gate via opening. the gate via opening exposes the metal gate layer. a portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. the gate via and contact openings merge to form a composite opening. a second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
Inventor(s): Jian-Jou Lian of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Bin Huang of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Neng-Jye Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Min Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/306, H01L21/48, H01L23/522, H01L23/532
CPC Code(s): H01L21/76823
Abstract: embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. in some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. the dielectric layer has a sidewall. the surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. the conductive feature is along the surface modification layer.
Inventor(s): Hsi-Wen Tien of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chieh Yao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Teng Dai of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hao Liao of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/311, H01L23/522, H01L27/092
CPC Code(s): H01L21/76831
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes an interconnect dielectric layer over a substrate. an interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. a protective layer surrounds the interconnect via. the interconnect via vertically extends through the protective layer to below a bottom of the protective layer. the protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.
Inventor(s): Yu-Jen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hua Feng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Yann HSIEH of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/485, H01L23/522, H01L23/532
CPC Code(s): H01L21/76846
Abstract: interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. an exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. the via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. the first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. the via bulk layer can include tungsten and/or cobalt. a capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. in some implementations, the capping layer includes cobalt and silicon.
Inventor(s): Ya-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsuan Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Yuan Ku of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ching Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H01L21/823437
Abstract: metal gate cutting techniques for fin-like field effect transistors (finfets) are disclosed herein. an exemplary method includes receiving an integrated circuit (ic) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. the gate structures traverses the fins and includes first and second gate structures. the method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
Inventor(s): Feng-Ching Chu of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/3065, H01L21/308, H01L27/092, H01L29/08, H01L29/66
CPC Code(s): H01L21/823814
Abstract: a semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate in the second region, and a second epitaxial feature over the second fin. the isolation feature includes a first portion disposed on sidewalls of the first fin, a second portion disposed on sidewalls of the second fin, and a third portion located between the first fin and the second fin. the third portion has a thickness larger than the first portion and the second portion.
Inventor(s): Meng-Liang Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao Chuang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Te-Chi Wong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shuo-Mao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/48, H01L25/00, H01L25/065
CPC Code(s): H01L23/3192
Abstract: a semiconductor package and a manufacturing method thereof are provided. the semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. the circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. the circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. a location of the metal floor plate corresponds to a location of the cavity. the metal floor plate is electrically floating and isolated by the dielectric material. the semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. the filling material is disposed between the semiconductor die and the circuit substrate. the filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
Inventor(s): Wen-Sheh Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Ping Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/8238, H01L23/31, H01L23/522, H01L23/528, H01L27/092, H01L29/06, H01L29/66, H01L29/775, H01L29/78
CPC Code(s): H01L23/367
Abstract: a device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. the second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. the thermal dissipation path comprises a dummy via.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: a method includes forming a plurality of semiconductor sheets on a front-side of a semiconductive layer; forming a gate strip surrounding each of the semiconductor sheets; forming a plurality of source/drain structures on either side of each of the semiconductor sheets; doping the semiconductive layer with a dopant, the dopant has a same conductivity type as the source/drain structures; forming a power supply voltage line on a back-side of the doped semiconductive layer.
Inventor(s): Hung-Chun Cho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/56, H01L21/768, H01L23/00, H01L23/31
CPC Code(s): H01L23/481
Abstract: a package structure and method of forming the same are provided. the package structure includes a die, a through via, an encapsulant, an adhesion promoter layer, an insulating layer and a polymer layer. the through via is laterally aside the die. the encapsulant laterally encapsulates the die and the a through via. the adhesion promoter layer and an insulating layer are sandwiched between the a through via and the encapsulant. sidewalls of the a through via are covered by the adhesion promoter layer and the insulating layer. the polymer layer is located under the through via and encapsulant. the insulating layer includes a plurality of portions.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/00, H01L23/48, H01L23/528, H01L25/065
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, a through substrate via (tsv) penetrating through the first semiconductor substrate and extending into the first interconnect structure, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the tsv through the first interconnect structure. the tsv includes a first surface in the first interconnect structure and a second surface opposite to the first surface, and the first bonding conductor includes a first bonding surface facing away the first interconnect structure. in a view, a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the tsv.
Inventor(s): Chih-Hsuan Tai of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Hsien Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chih Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ban-Li Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Cheng Tseng of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/367, H01L23/48, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. an outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. the die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.
Inventor(s): Chia-Wei Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Hsu Wu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Ping Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih Wei LU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsi-Wen Tien of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Cherng-Shiaw Tsai of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/311, H01L21/768, H01L23/522
CPC Code(s): H01L23/528
Abstract: a method of forming a semiconductor device includes the following operations. a substrate is provided with an electric component. a composite dielectric layer is formed on the substrate and covers the electric component. an opening is formed through the composite dielectric layer. a directional etching process is performed to widen an upper portion of the opening. a metal feature is formed in the opening.
Inventor(s): Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/288, H01L21/48, H01L21/56, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L23/50, H01L25/00, H01L25/065, H01L25/10, H01L25/16
CPC Code(s): H01L23/5389
Abstract: in an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.
Inventor(s): Sen-Kuei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/66, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/522
CPC Code(s): H01L23/66
Abstract: a package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. the semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. the waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. the antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
Inventor(s): Jen-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
CPC Code(s): H01L25/0652
Abstract: a semiconductor package includes: a base substrate structure; and a plurality of die groups disposed on a top surface of the based substrate structure, the plurality of die groups comprising a first die group and a second die group neighboring to each other. the first die group includes a plurality of first dies stacked parallel to each other and parallel to a front surface of the first die group, the front surface of the first die group and the top surface intersect at a first edge extending in a first direction. the second die group includes a plurality of second dies stacked parallel to each other and parallel to a front surface of the second die group, the front surface of the second die group and the top surface intersect at a second edge extending in a second direction not parallel to the first direction.
Inventor(s): Chin-Min Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jen Hsu of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, G02B6/42, G02B6/43, H01L21/48, H01L23/522, H01L23/538
CPC Code(s): H01L25/0657
Abstract: semiconductor devices and methods of forming the same are provided. a method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (eics), forming a second wafer including a plurality of photonic integrated circuits (pics), bonding the first wafer to the second wafer to form a first stacked wafer. the bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the eics with one of the plurality of the pics.
Inventor(s): Chung-Chieh YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ting LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L21/768, H01L21/8238, H01L23/522
CPC Code(s): H01L27/0207
Abstract: a device includes an electrical circuit. the device further includes a first conductive pillar over a first side of a substrate. the device further includes a first conductive rail electrically connected to the first conductive pillar, wherein the electrical circuit is electrically connected to the first conductive rail by the first conductive pillar. the device further includes a power pillar extending through the substrate, wherein the power pillar is electrically connected to the first conductive rail.
Inventor(s): Shi-Ning JU of Hsin Chiu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/762, H01L21/8234, H01L29/08, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L27/0886
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes multiple semiconductor nanostructures and a gate stack wrapped around the semiconductor nanostructures. the semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching one or more of the semiconductor nanostructures. the semiconductor device structure further includes an isolation structure continuously extending across edges of the semiconductor nanostructures.
Inventor(s): Kuo-Cheng CHING of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/02, H01L21/027, H01L21/033, H01L21/3105, H01L21/311, H01L21/3213, H01L21/762, H01L21/8234, H01L27/02, H01L29/08, H01L29/165, H01L29/205, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. the first dielectric layer is laterally between the first and second semiconductive fins. from a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a u-shaped profile. the first gate structure extends across the first and second semiconductive fins and the first dielectric layer. the spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. the oxide material is nested in the first dielectric layer. a top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.
Inventor(s): Jia-Chuan You of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/423, H01L29/786
CPC Code(s): H01L27/0886
Abstract: a semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.
Inventor(s): Wei-Chih HOU of Hsinchu city (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Jun LIN of Hsinchu city (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Ming CHANG of Taitung city (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Ning HSU of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L27/0922
Abstract: a method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers.
Inventor(s): Yu-Wei Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hsien Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14636
Abstract: some embodiments relate to an integrated chip including a semiconductor substrate and a pixel array comprising a plurality of photodetectors in the semiconductor substrate. the pixel array further comprises a plurality of transistors on a frontside of the semiconductor substrate. a backside ground (bsgd) structure extends into a backside of the semiconductor substrate, opposite the frontside, and further surrounding the pixel array along a periphery of the pixel array. the bsgd structure has a first sloped sidewall extending from a bottom surface of the bsgd structure that is recessed into the semiconductor substrate.
Inventor(s): Chun-Hsiung Tsai of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd., Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Clement Hsingjen Wann of Carmel NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B12/00, H01L23/00, H01L23/522, H01L23/528, H01L27/146, H01L29/94
CPC Code(s): H01L28/60
Abstract: a semiconductor device and a method of forming the same are provided. the semiconductor device includes a substrate, a deep trench capacitor (dtc) having a portion within the substrate, and an interconnect structure over the dtc and the substrate. the interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the dtc, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
Inventor(s): Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Te-Hsin Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L23/522, H01L25/11, H01L29/423, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. in one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.
20240194749.SEMICONDUCTOR DEVICES_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Sai-Hooi Yeong of Perdana (MY) for taiwan semiconductor manufacturing co., ltd., Pei-Yu Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/306, H01L21/3065, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/41733
Abstract: in an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.
Inventor(s): Yi-Hsiu Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Andrew Joseph Kelly of Hengshan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/306, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/41791
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. a backside contact is arranged below and coupled to the first source/drain region. the backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.
Inventor(s): Yu-Xuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hou-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Ting CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jin CAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. the stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. the first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. the first and second layers can be selectively removed and replaced with inner spacers. the second layer can be selectively removed and replaced with a gate electrode.
Inventor(s): Zhi-Chang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Cheng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Hung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Ning YAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/40, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. the method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. the method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
Inventor(s): Chih-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yi PENG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang LEE of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Pin LIN of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/49, H01L21/28, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/4991
Abstract: some implementations described herein provide a semiconductor device and methods of formation. the semiconductor device includes a gate-all-around transistor having one or more dielectric regions that include or more dielectric gases. the dielectric regions may include a first dielectric region between epitaxial regions (e.g., source/drain regions) and a first portion of a gate structure of the gate-all-around transistor. the dielectric regions may further include a second dielectric region between a contact structure of gate-all-around transistor and a second portion of the gate structure. by including the dielectric regions in the gate-all-around transistor, a parasitic capacitance associated with the gate-all-around transistor may be reduced relative to another gate-all-around transistor not including the dielectric regions.
Inventor(s): Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pei-Yu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/51, H01L21/02, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/516
Abstract: the present disclosure provides a method of forming a semiconductor device including an nfet structure and a pfet structure where each of the nfet and pfet structures include a semiconductor substrate and a gate trench. the method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nfet structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pfet structure, and depositing a gate electrode in each gate trench.
Inventor(s): Chih-Ching Wang of Kinmen County (TW) for taiwan semiconductor manufacturing co., ltd., Jon-Hsu Ho of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsing Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Wei Wu of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd., Zhiqiang Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/78
CPC Code(s): H01L29/66484
Abstract: a semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (s/d) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the s/d epitaxial layer and the gate dielectric layer. the dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. the first dielectric layer has a dielectric constant higher than that of the second dielectric layer. the second dielectric layer separates the first dielectric layer from physically contacting the s/d epitaxial layer.
Inventor(s): Yoh-Rong Liu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Kai Lin of Yilan County (TW) for taiwan semiconductor manufacturing co., ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chi Yu of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Sen-Hong Syue of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/423, H01L29/786
CPC Code(s): H01L29/66553
Abstract: a method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. the sidewalls are adjacent to the first recess. the method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
Inventor(s): Hsiao-Chun CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Jie Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/78
CPC Code(s): H01L29/66795
Abstract: the present disclosure describes a semiconductor structure and a method for forming the same. the semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. the epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. a lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.
Inventor(s): Jen-Hong Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Yi Chao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Cheng Chao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., You-Ting Lin of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chung Chang of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsiu Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Ming Kuo of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sung-En Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/06, H01L29/78
CPC Code(s): H01L29/66795
Abstract: semiconductor structures and methods of forming the same are provided. a method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.
Inventor(s): Gulbagh SINGH of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hsin-Chi Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Tsang Chuang of Maoli (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/265, H01L21/3065, H01L21/762
CPC Code(s): H01L29/7846
Abstract: the present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (sige) epitaxial layers. the method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form ge-doped regions that extend from the semiconductor layer to the isolation region. the method further includes disposing second photoresist structures over the isolation region and etching exposed ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the ge-doped regions in the isolation region. finally the method includes growing a sige epitaxial stack in the openings.
20240194785.FINFET DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chia Tai Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Yih-Ann Lin of Jhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., An-Shen Chang of Jubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Chiayi (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Cheng Chen of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L21/84, H01L29/40, H01L29/66
CPC Code(s): H01L29/785
Abstract: a fin-type field-effect transistor (finfet) device includes a plurality of fins formed over a substrate. the semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. the dielectric trench has a vertical profile. the semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. the second portion of the plurality of fins have a rounded-convex-shape top profile.
Inventor(s): Cheng-Ting Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/04, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/7855
Abstract: a semiconductor device according to the present disclosure includes a first transistor and a second transistor. the first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. the second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. each of the plurality of first channel members has a first width and a first height smaller than the first width. each of the plurality of second channel members has a second width and a second height greater than the second width.
Inventor(s): Chien-Chang SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yan-Ting LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Wei LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Bang-Ting YAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih Teng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Chiang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-I KUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Horng LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia YEO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L29/06, H01L29/165, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/78618
Abstract: a method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.
Inventor(s): Katherine H. CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Neil Quinn MURRAY of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Yen CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L29/423
CPC Code(s): H01L29/78696
Abstract: a transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a uv-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by uv light.
Inventor(s): Feng-Ming Chang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Hsiu Hsu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, H01L21/768, H01L23/485, H01L27/02, H10B99/00
CPC Code(s): H10B10/12
Abstract: systems and methods are provided for forming an intra-connection structure. a first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. a first dielectric material is disposed on the first source/drain region. a spacer material is formed on the first gate structure. the first dielectric material is removed to expose at least part of the first source/drain region. at least part of the spacer material is removed to expose at least part of the first gate structure. a first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
Inventor(s): Chen-Feng Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Min Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hengyuan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/20, H10B63/00, H10N70/00
CPC Code(s): H10N70/231
Abstract: a memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. the memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
Inventor(s): Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Jiun Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Ming Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00, H01L23/528, H10B63/00, H10N70/20
CPC Code(s): H10N70/826
Abstract: a memory cell includes a memory device, a connecting structure, an insulating layer and a selector. the connecting structure is disposed on and electrically connected to the memory device. the insulating layer covers the memory device and the connecting structure. the selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on June 13th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B65B5/04
- B65G47/28
- G01N21/95
- G06T7/00
- CPC B65B5/045
- Taiwan semiconductor manufacturing co., ltd.
- B81C1/00
- H01L21/02
- H01L21/3105
- H01L21/66
- CPC B81C1/00238
- G02B6/43
- G02B6/42
- CPC G02B6/43
- G03F1/24
- CPC G03F1/24
- G03F1/66
- G03F7/00
- H01L21/027
- H01L21/673
- CPC G03F1/66
- G03F7/11
- G03F7/09
- CPC G03F7/11
- G06F1/20
- G06F1/04
- CPC G06F1/206
- G06F3/06
- CPC G06F3/0653
- G06F30/398
- G06F30/392
- CPC G06F30/398
- G11C8/08
- G11C29/02
- G11C29/12
- G11C29/50
- H01L21/822
- CPC G11C8/08
- G11C13/00
- CPC G11C13/003
- H01L21/265
- H01L29/40
- H01L29/66
- CPC H01L21/02321
- H01L21/48
- C25D3/38
- C25D7/12
- H01L21/56
- CPC H01L21/486
- H01L21/68
- G01B7/31
- CPC H01L21/681
- H01L21/768
- H01L21/321
- H01L21/8234
- H01L29/08
- H01L29/417
- H01L29/423
- H01L29/49
- CPC H01L21/76807
- H01L21/306
- H01L23/522
- H01L23/532
- CPC H01L21/76823
- H01L21/311
- H01L27/092
- CPC H01L21/76831
- H01L23/485
- CPC H01L21/76846
- H01L27/088
- CPC H01L21/823437
- H01L21/8238
- H01L21/3065
- H01L21/308
- CPC H01L21/823814
- H01L23/31
- H01L23/00
- H01L23/48
- H01L25/00
- H01L25/065
- CPC H01L23/3192
- H01L23/367
- H01L23/528
- H01L29/06
- H01L29/775
- H01L29/78
- CPC H01L23/367
- H01L29/786
- CPC H01L23/481
- CPC H01L23/5226
- CPC H01L23/528
- H01L23/538
- H01L21/288
- H01L21/683
- H01L23/50
- H01L25/10
- H01L25/16
- CPC H01L23/5389
- H01L23/66
- CPC H01L23/66
- CPC H01L25/0652
- CPC H01L25/0657
- H01L27/02
- CPC H01L27/0207
- H01L21/762
- CPC H01L27/0886
- H01L21/033
- H01L21/3213
- H01L29/165
- H01L29/205
- CPC H01L27/0922
- H01L27/146
- CPC H01L27/14636
- H10B12/00
- H01L29/94
- CPC H01L28/60
- H01L25/11
- CPC H01L29/0673
- CPC H01L29/41733
- CPC H01L29/41791
- CPC H01L29/42392
- H01L21/28
- CPC H01L29/4991
- H01L29/51
- CPC H01L29/516
- CPC H01L29/66484
- CPC H01L29/66553
- CPC H01L29/66795
- CPC H01L29/7846
- H01L21/84
- CPC H01L29/785
- H01L29/04
- H01L29/10
- CPC H01L29/7855
- CPC H01L29/78618
- CPC H01L29/78696
- H10B10/00
- H10B99/00
- CPC H10B10/12
- H10N70/20
- H10B63/00
- H10N70/00
- CPC H10N70/231
- CPC H10N70/826