Micron technology, inc. (20240176697). Controller-Level Memory Repair simplified abstract
Contents
- 1 Controller-Level Memory Repair
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Controller-Level Memory Repair - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
Controller-Level Memory Repair
Organization Name
Inventor(s)
Smruti Subhash Jhaveri of Boise ID (US)
Controller-Level Memory Repair - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240176697 titled 'Controller-Level Memory Repair
Simplified Explanation
The patent application describes apparatuses and methods for sharing redundant memory portions at a controller-level to enable memory repair between multiple memory blocks. The controller can borrow spare rows from one memory die to repair faults in another memory die.
- Memory dies can have multiple spare rows for repairing faulty bits.
- Controller inventories unrepaired faults and available spare rows across memory dies.
- Controller can borrow spare rows from one memory die to repair faults in another.
- Memory access requests can be remapped to spare rows for repair.
Potential Applications
This technology can be applied in:
- Data centers
- High-performance computing
- Embedded systems
Problems Solved
- Memory faults in memory dies
- Efficient memory repair
- Improved memory reliability
Benefits
- Enhanced memory repair capabilities
- Increased memory reliability
- Cost-effective memory maintenance
Potential Commercial Applications
Optimized Memory Repair Technology for Enhanced Reliability
Possible Prior Art
No prior art known at this time.
Unanswered Questions
How does the controller prioritize which memory die to borrow spare rows from?
The patent application does not specify the criteria used by the controller to determine which memory die to borrow spare rows from.
What impact does sharing spare rows have on memory access latency?
The document does not address how sharing spare rows between memory dies may affect memory access latency.
Original Abstract Submitted
described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. if a memory die has more faults than spare rows, the memory die cannot repair the additional faults. this document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. the controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. the controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.
