Category:Frederick A. WARE of Los Altos Hills CA (US)

Frederick A. WARE of Los Altos Hills CA (US)

Executive Summary

Frederick A. WARE of Los Altos Hills CA (US) is an inventor who has filed 5 patents. Their primary areas of innovation include {Management of blocks} (2 patents), Timing circuits (for regeneration management (2 patents), Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management (2 patents), and they have worked with companies such as Rambus Inc. (5 patents). Their most frequent collaborators include (1 collaborations), (1 collaborations), (1 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• G06F3/064 ({Management of blocks}): 2 patents
• G11C11/4076 (Timing circuits (for regeneration management): 2 patents
• G11C7/22 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management): 2 patents
• G06F1/3287 (by switching off individual functional units in the computer system): 1 patents
• G06F1/3253 (Means for saving power): 1 patents
• G06F1/3278 (Means for saving power): 1 patents
• G06F1/3293 (Means for saving power): 1 patents
• G06F13/1694 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• Y02D10/00 (No explanation available): 1 patents
• G06F11/0727 ({in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units): 1 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 1 patents
• G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 1 patents
• G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0751 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/076 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0793 ({Remedial or corrective actions (recovery from an exception in an instruction pipeline): 1 patents
• G06F11/10 (Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's): 1 patents
• G06F11/1004 ({to protect a block of data words, e.g. CRC or checksum (): 1 patents
• G06F11/1008 ({in individual solid state devices (): 1 patents
• G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 1 patents
• G06F11/1402 ({Saving, restoring, recovering or retrying}): 1 patents
• G06F13/4286 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• H03M13/09 (Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit): 1 patents
• H03M13/29 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H03M13/2906 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H03M13/611 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H04L1/0061 ({Trellis-coded modulation}): 1 patents
• H04L1/08 (by repeating transmission, e.g. Verdan system {(): 1 patents
• H04L1/1867 (Automatic repetition systems, e.g. Van Duuren systems): 1 patents
• G06F11/1044 ({with specific ECC/EDC distribution}): 1 patents
• H04L1/0003 ({by switching between different modulation schemes}): 1 patents
• H04L1/0008 (Arrangements for detecting or preventing errors in the information received {(correcting synchronisation): 1 patents
• H04L2001/0093 (TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication): 1 patents
• G06F1/04 (Generating or distributing clock signals or signals derived directly therefrom): 1 patents
• G06F13/4243 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• G11C7/1093 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/222 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management): 1 patents
• G11C7/04 (with means for avoiding disturbances due to temperature effects): 1 patents
• G06F3/0611 ({in relation to response time}): 1 patents
• G06F3/0625 ({Power saving in storage systems}): 1 patents
• G06F3/0655 ({Replication mechanisms}): 1 patents
• G06F3/0673 ({Single storage device}): 1 patents
• G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 1 patents
• G11C7/06 (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 1 patents
• G11C7/18 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C11/4097 (Bit-line organisation, e.g. bit-line layout, folded bit lines): 1 patents
• G06F11/1076 ({Parity data used in redundant arrays of independent storages, e.g. in RAID systems}): 1 patents
• G06F11/1048 ({using arrangements adapted for a specific error detection or correction feature}): 1 patents

Companies

List of Companies

• Rambus Inc.: 5 patents

Collaborators

• Yuanlong WANG of San Jose CA (US) (1 collaborations)
• Jared L. ZERBE of Woodside CA (US) (1 collaborations)
• John Eric LINSTADT of Palo Alto CA (US) (1 collaborations)
• Brent S. HAUKNESS of Sunnyvale CA (US) (1 collaborations)
• Lawrence LAI of San Jose CA (US) (1 collaborations)