ATOMERA INCORPORATED patent applications published on September 26th, 2024
Contents
- 1 Patent applications for ATOMERA INCORPORATED on September 26th, 2024
- 1.1 RADIO FREQUENCY (RF) SEMICONDUCTOR DEVICES INCLUDING A GROUND PLANE LAYER HAVING A SUPERLATTICE (18669156)
- 1.2 NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613509)
- 1.3 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613356)
- 1.4 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613435)
- 1.5 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613557)
- 1.6 NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613401)
- 1.7 NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613476)
Patent applications for ATOMERA INCORPORATED on September 26th, 2024
RADIO FREQUENCY (RF) SEMICONDUCTOR DEVICES INCLUDING A GROUND PLANE LAYER HAVING A SUPERLATTICE (18669156)
Main Inventor
HIDEKI TAKEUCHI
NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613509)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613356)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613435)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613557)
Main Inventor
Donghun Kang
NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613401)
Main Inventor
Donghun Kang
NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613476)
Main Inventor
Donghun Kang
