ATOMERA INCORPORATED patent applications published on September 26th, 2024
Summary of the patent applications from ATOMERA INCORPORATED on September 26th, 2024
1. **Summary**: ATOMERA INCORPORATED has recently filed patents for semiconductor devices featuring gate stacks with alternating layers of different semiconductor materials, including nanostructures, source/drain regions, insulating regions, and dopant blocking superlattices. These innovations aim to enhance the performance and efficiency of semiconductor devices, improve doping control, and facilitate the fabrication of nanostructures.
2. **Key Points of Patents**:
- Gate stacks with alternating semiconductor materials and nanostructures.
- Source/drain regions within trenches.
- Insulating regions adjacent to layers of the first semiconductor material.
- Dopant blocking superlattices adjacent to nanostructures.
- Dopant blocking superlattices composed of stacked groups of layers.
3. **Notable Applications**:
- Advanced semiconductor devices for high-performance electronics.
- Nanotechnology applications for nanostructure fabrication.
- Improved doping control in semiconductor manufacturing processes.
Contents
- 1 Patent applications for ATOMERA INCORPORATED on September 26th, 2024
- 1.1 RADIO FREQUENCY (RF) SEMICONDUCTOR DEVICES INCLUDING A GROUND PLANE LAYER HAVING A SUPERLATTICE (18669156)
- 1.2 NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613509)
- 1.3 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613356)
- 1.4 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613435)
- 1.5 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613557)
- 1.6 NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613401)
- 1.7 NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613476)
Patent applications for ATOMERA INCORPORATED on September 26th, 2024
RADIO FREQUENCY (RF) SEMICONDUCTOR DEVICES INCLUDING A GROUND PLANE LAYER HAVING A SUPERLATTICE (18669156)
Main Inventor
HIDEKI TAKEUCHI
NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613509)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613356)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613435)
Main Inventor
Donghun Kang
METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS (18613557)
Main Inventor
Donghun Kang
NANOSTRUCTURE TRANSISTORS WITH FLUSH SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613401)
Main Inventor
Donghun Kang
NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE (18613476)
Main Inventor
Donghun Kang
