18815521. 3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT (Micron Technology, Inc.)
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3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
Organization Name
Inventor(s)
Tony M. Brewer of Plano TX (US)
3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
This abstract first appeared for US patent application 18815521 titled '3D STACKED INTEGRATED CIRCUITS HAVING FAILURE MANAGEMENT
Original Abstract Submitted
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
