18615691. HANDLING MEMORY REQUESTS simplified abstract (Imagination Technologies Limited)

HANDLING MEMORY REQUESTS

Organization Name

Imagination Technologies Limited

Inventor(s)

Mark Landers of Hertfordshire (GB)

Martin John Robinson of Hertfordshire (GB)

HANDLING MEMORY REQUESTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18615691 titled 'HANDLING MEMORY REQUESTS

The abstract describes a converter module that handles memory requests from a cache, tracks the status of these requests using transaction identifiers, and sends requests for address translation to a memory management unit.

• Memory requests are issued with transaction identifiers to track their status.
• Address translation requests are sent to a memory management unit.
• Memory requests are prioritized based on the source (cache or memory management unit).
• Transaction identifiers are freed once a response is received from the memory.
• The converter module interfaces with the memory via a bus for memory requests.

Potential Applications: - This technology can be used in microprocessor systems to efficiently handle memory requests. - It can improve the performance of on-chip caches by optimizing memory access.

Problems Solved: - Efficient handling of memory requests from caches. - Tracking the status of memory requests using transaction identifiers. - Prioritizing memory requests based on the source.

Benefits: - Improved memory access efficiency. - Enhanced performance of on-chip caches. - Streamlined memory request handling process.

Commercial Applications: Title: "Efficient Memory Request Handling Technology for Microprocessor Systems" This technology can be applied in microprocessor systems, data centers, and embedded systems to optimize memory access and enhance overall system performance. It can be marketed to semiconductor companies, system integrators, and technology firms looking to improve memory management in their products.

Questions about the technology: 1. How does the converter module prioritize memory requests from different sources? 2. What are the potential challenges in implementing this technology in complex microprocessor systems?

Original Abstract Submitted

A converter module handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.