18409620. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to existing semiconductor packaging methods?
- 1.11 What are the specific electronic devices that could benefit most from this technology?
- 1.12 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Shih-Ting Hung of New Taipei City (TW)
Meng-Liang Lin of Hsinchu (TW)
Yi-Wen Wu of New Taipei City (TW)
Po-Yao Chuang of Hsin-Chu (TW)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18409620 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a redistribution structure with a first conductive pad, first and second conductive vias, and a first dielectric layer. The encapsulated die is electrically connected to the redistribution structure. The first conductive pad has opposing sides, with the first conductive via landing on one side and the second conductive via landing on the other side. The first dielectric layer covers the first conductive pad and the vias.
- The semiconductor package includes a redistribution structure with a first conductive pad, first and second conductive vias, and a first dielectric layer.
- The first conductive pad has opposing sides, with the first conductive via landing on one side and the second conductive via landing on the other side.
- The first dielectric layer covers the first conductive pad and the vias.
Potential Applications
The technology described in this patent application could be applied in the manufacturing of advanced semiconductor packages for various electronic devices, such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficiently connecting an encapsulated die to a redistribution structure in a semiconductor package, ensuring reliable electrical connections and optimal performance.
Benefits
The benefits of this technology include improved electrical connectivity, enhanced performance, and increased reliability of semiconductor packages in electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology could be in the semiconductor industry for the production of high-performance electronic devices with advanced packaging technology.
Possible Prior Art
One possible prior art for this technology could be the use of similar redistribution structures and encapsulated dies in semiconductor packages for electronic devices.
Unanswered Questions
How does this technology compare to existing semiconductor packaging methods?
This article does not provide a direct comparison to existing semiconductor packaging methods, leaving the reader to wonder about the specific advantages and disadvantages of this new technology in relation to current practices.
What are the specific electronic devices that could benefit most from this technology?
The article does not specify the electronic devices that could benefit most from this technology, leaving the reader to speculate on which products would see the greatest improvements with the implementation of this semiconductor packaging innovation.
Original Abstract Submitted
A semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. The redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. The first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. The second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. The first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. The encapsulated die is disposed below the first side of the first conductive via.
