18302276. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Jongcheol Kim of Suwon-si (KR)
Hyongryol Hwang of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18302276 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The semiconductor memory device described in the patent application includes a memory cell array with multiple memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each memory cell row as count data. It performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row, update the count data, and write the updated count data back into the count cells of the target row. The row hammer management circuit also includes a hammer address queue and randomly changes the updated count data based on an event signal indicating a state change of the hammer address queue.
- The memory device has a memory cell array with multiple rows and a row hammer management circuit.
- The row hammer management circuit stores counted values in count cells of each memory cell row as count data.
- It performs an internal read-update-write operation to read and update the count data of a target memory cell row.
- The updated count data is then written back into the count cells of the target row.
- The row hammer management circuit includes a hammer address queue.
- The updated count data is randomly changed based on an event signal indicating a state change of the hammer address queue.
Potential applications of this technology:
- Memory devices with improved row hammer management capabilities.
- Enhanced performance and reliability of semiconductor memory systems.
- Prevention of row hammer-induced errors in memory cell arrays.
Problems solved by this technology:
- Row hammer-induced errors in memory cell arrays.
- Inefficient management of count data in memory cell rows.
- Lack of randomization in count data updates.
Benefits of this technology:
- Improved reliability and performance of memory cell arrays.
- Enhanced protection against row hammer-induced errors.
- Efficient management of count data in memory cell rows.
- Randomization of count data updates for better security.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.
