17884695. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Minsoo Kim of Hwaseong-si (KR)
Unbyoung Kang of Hwaseong-si (KR)
Sangsick Park of Hwaseong-si (KR)
Teakhoon Lee of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17884695 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes two semiconductor chips stacked on top of each other.
- The first chip has upper signal pads and upper dummy pads, while the second chip has lower signal pads and lower dummy pads.
- Conductive bumps are used to connect the upper signal pads to the lower signal pads, and separate conductive bumps are used to connect the upper dummy pads to the lower dummy pads.
- The upper dummy pads include merged pads that cover multiple adjacent lower dummy pads.
- Each merged pad has multiple metal plating layers corresponding to the adjacent lower dummy pads.
- The second conductive bumps are placed between the first metal plating layers and the adjacent lower dummy pads.
Potential applications of this technology:
- Semiconductor packaging for electronic devices
- Integrated circuits and microprocessors
Problems solved by this technology:
- Efficient use of space in semiconductor packaging
- Improved electrical connectivity between stacked chips
Benefits of this technology:
- Reduced size and weight of semiconductor packages
- Enhanced performance and reliability of electronic devices
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip including upper signal pads and upper dummy pads. A second semiconductor chip is on the first semiconductor chip, and includes lower signal pads and lower dummy pads. First conductive bumps are between the upper signal pads and the lower signal pads. Second conductive bumps are between the upper dummy pads and the lower dummy pads. The upper dummy pads include merged pads covering a plurality of adjacent lower dummy pads. A plurality of metal plating layers are disposed on each of the merged pads in areas respectively corresponding to the plurality of adjacent lower dummy pads. The second conductive bumps include a plurality of conductive bumps respectively disposed between the plurality of first metal plating layers and the plurality of adjacent lower dummy pads.
