17836142. SEMICONDUCTOR PACKAGES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGES
Organization Name
Inventor(s)
Juhyeon Kim of Cheonan-si (KR)
Sunkyoung Seo of Cheonan-si (KR)
SEMICONDUCTOR PACKAGES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17836142 titled 'SEMICONDUCTOR PACKAGES
Simplified Explanation
The abstract describes a semiconductor package that includes multiple semiconductor chips and a redistribution substrate. The first semiconductor chip is placed on the redistribution substrate, and the second semiconductor chip is positioned between the redistribution substrate and the first semiconductor chip. The second chip is narrower than the first chip and includes various layers and alignment key patterns.
- The semiconductor package includes a redistribution substrate, first and second semiconductor chips.
- The second semiconductor chip is narrower than the first semiconductor chip.
- The first semiconductor chip has an alignment key pattern on its bottom surface.
- The second semiconductor chip has a second interconnection layer, a second semiconductor substrate, and a second alignment key pattern.
Potential applications of this technology:
- Integrated circuits and electronic devices manufacturing.
- Semiconductor packaging industry.
- Consumer electronics, such as smartphones, tablets, and laptops.
Problems solved by this technology:
- Efficient utilization of space in semiconductor packages.
- Improved alignment and positioning of semiconductor chips.
- Enhanced electrical connectivity between chips.
Benefits of this technology:
- Compact and space-saving design.
- Improved performance and reliability of semiconductor packages.
- Simplified manufacturing process.
- Enhanced electrical and mechanical connectivity between chips.
Original Abstract Submitted
A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.
