17830042. DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES
Organization Name
Inventor(s)
Lorenzo Fratin of Buccinasco (MI) (IT)
Fabio Pellizzer of Boise ID (US)
Paolo Fantini of Vimercate (MB) (IT)
DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17830042 titled 'DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY DEVICES
Simplified Explanation
The abstract describes a patent application for decoder architectures for three-dimensional memory devices. The decoder includes two portions - a first portion manufactured on top of the memory array and a second portion implemented in a separate semiconductor device. The first portion includes a pillar decoding portion and a word line decoding portion, while the second portion includes logic circuits to drive signals to contacts of the first portion.
- The decoder architecture is designed for three-dimensional memory devices.
- It includes two portions - one on top of the memory array and another in a separate semiconductor device.
- The first portion includes a pillar decoding portion and a word line decoding portion.
- The second portion includes logic circuits to drive signals to contacts of the first portion.
Potential Applications
- Three-dimensional memory devices
- Semiconductor devices
Problems Solved
- Efficient decoding of memory arrays in three-dimensional memory devices
- Integration of separate semiconductor devices with memory arrays
Benefits
- Improved performance and efficiency in three-dimensional memory devices
- Simplified integration of separate semiconductor devices with memory arrays
Original Abstract Submitted
Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.
