17804826. DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE simplified abstract (Micron Technology, Inc.)

From WikiPatents
Jump to navigation Jump to search

DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE

Organization Name

Micron Technology, Inc.

Inventor(s)

Nitul Gohain of Bangalore (IN)

Giuseppe Cariello of Boise ID (US)

Jameer Mulani of Bangalore (IN)

DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17804826 titled 'DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE

Simplified Explanation

The patent application describes methods, systems, and devices for determining memory locations for boot-up code. It involves receiving an indication of timeout durations for a boot sequence and storing information for the boot sequence in memory cells based on these durations. The selection of memory cells is based on factors such as read latency, error rate, and storage-level. The stored information is accessed during the initialization of the boot sequence.

  • The patent application focuses on determining memory locations for boot-up code.
  • It involves receiving timeout durations for a boot sequence.
  • Information for the boot sequence is stored in memory cells based on the timeout durations.
  • The selection of memory cells is based on factors like read latency, error rate, and storage-level.
  • The stored information is accessed during the initialization of the boot sequence.

Potential Applications

This technology has potential applications in various fields, including:

  • Computer systems and servers
  • Embedded systems and IoT devices
  • Mobile devices and smartphones
  • Automotive electronics and infotainment systems
  • Industrial control systems and automation

Problems Solved

The technology addresses the following problems:

  • Efficient determination of memory locations for boot-up code
  • Optimizing storage and retrieval of boot sequence information
  • Minimizing read latency and error rates during boot-up
  • Enhancing the reliability and performance of boot sequences

Benefits

The technology offers several benefits, including:

  • Improved boot-up speed and efficiency
  • Enhanced reliability and error handling during boot sequences
  • Optimal utilization of memory cells based on timeout durations
  • Increased performance and responsiveness of systems during initialization.


Original Abstract Submitted

Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.