Kioxia corporation (20240320091). MEMORY SYSTEM simplified abstract
Contents
MEMORY SYSTEM
Organization Name
Inventor(s)
Masanobu Shirakawa of Chigasaki (JP)
MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240320091 titled 'MEMORY SYSTEM
The memory system described in the abstract consists of a memory and a memory controller, with the controller including an encoder that generates codewords from data sections.
- The encoder creates a first codeword with error correction code parity based on the rank of the data sections, with each codeword containing bit strings associated with columns and rows.
- The memory controller writes these bit strings into magnetic bodies, ensuring each body contains a unique bit string.
Potential Applications: - Data storage systems - Error correction in memory systems - Magnetic memory technologies
Problems Solved: - Error correction in memory systems - Efficient data storage and retrieval
Benefits: - Improved data integrity - Enhanced memory system performance - Increased reliability in data storage
Commercial Applications: Title: "Enhanced Memory Systems for Data Storage" This technology can be utilized in: - Data centers - Cloud storage services - Consumer electronics
Questions about the technology: 1. How does the error correction code parity improve data integrity in memory systems? 2. What are the advantages of using magnetic bodies for data storage in this memory system?
Frequently Updated Research: Stay updated on advancements in error correction codes for memory systems and magnetic memory technologies.
Original Abstract Submitted
a memory system includes a memory and a memory controller. the memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. the first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. the first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. the first bit strings each include a plurality of bits respectively associated with a plurality of rows. the memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.
