Difference between revisions of "SanDisk Technologies LLC patent applications published on November 30th, 2023"
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− | + | ==Patent applications for SanDisk Technologies LLC on November 30th, 2023== | |
+ | |||
+ | ===CHIP SELECT, COMMAND, AND ADDRESS ENCODING ([[US Patent Application 17828921. CHIP SELECT, COMMAND, AND ADDRESS ENCODING simplified abstract (SanDisk Technologies LLC)|17828921]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | TIANYU TANG | ||
+ | |||
+ | |||
+ | ===CROSS-POINT ARRAY REFRESH SCHEME ([[US Patent Application 17824806. CROSS-POINT ARRAY REFRESH SCHEME simplified abstract (SanDisk Technologies LLC)|17824806]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Michael Nicolas Albert Tran | ||
+ | |||
+ | |||
+ | ===HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825048. HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract (SanDisk Technologies LLC)|17825048]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Xiang Yang | ||
+ | |||
+ | |||
+ | ===LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES ([[US Patent Application 17825193. LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract (SanDisk Technologies LLC)|17825193]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Xiang Yang | ||
+ | |||
+ | |||
+ | ===NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION ([[US Patent Application 17825337. NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION simplified abstract (SanDisk Technologies LLC)|17825337]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shiqian Shao | ||
+ | |||
+ | |||
+ | ===METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING ([[US Patent Application 17824350. METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING simplified abstract (SanDisk Technologies LLC)|17824350]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Peng Wang | ||
+ | |||
+ | |||
+ | ===SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES ([[US Patent Application 17827562. SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES simplified abstract (SanDisk Technologies LLC)|17827562]])=== | ||
+ | |||
− | + | '''Main Inventor''' | |
− | + | Venkatesh Prasad RAMACHANDRA | |
− | |||
− | + | ===NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT ([[US Patent Application 17828685. NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT simplified abstract (SanDisk Technologies LLC)|17828685]])=== | |
− | |||
− | + | '''Main Inventor''' | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
+ | Jiacen Guo | ||
+ | ===TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE ([[US Patent Application 17826434. TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE simplified abstract (SanDisk Technologies LLC)|17826434]])=== | ||
− | ==Patent | + | |
+ | '''Main Inventor''' | ||
+ | |||
+ | Sujjatul Islam | ||
+ | |||
+ | |||
+ | ===SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES ([[US Patent Application 17828708. SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES simplified abstract (SanDisk Technologies LLC)|17828708]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jang Woo Lee | ||
+ | |||
+ | |||
+ | ===THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME ([[US Patent Application 17804184. THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME simplified abstract (SanDisk Technologies LLC)|17804184]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Akihiro TOBIOKA |
Revision as of 08:56, 6 December 2023
Contents
- 1 Patent applications for SanDisk Technologies LLC on November 30th, 2023
- 1.1 CHIP SELECT, COMMAND, AND ADDRESS ENCODING (17828921)
- 1.2 CROSS-POINT ARRAY REFRESH SCHEME (17824806)
- 1.3 HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825048)
- 1.4 LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825193)
- 1.5 NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION (17825337)
- 1.6 METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING (17824350)
- 1.7 SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES (17827562)
- 1.8 NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT (17828685)
- 1.9 TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE (17826434)
- 1.10 SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES (17828708)
- 1.11 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME (17804184)
Patent applications for SanDisk Technologies LLC on November 30th, 2023
CHIP SELECT, COMMAND, AND ADDRESS ENCODING (17828921)
Main Inventor
TIANYU TANG
CROSS-POINT ARRAY REFRESH SCHEME (17824806)
Main Inventor
Michael Nicolas Albert Tran
HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825048)
Main Inventor
Xiang Yang
LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES (17825193)
Main Inventor
Xiang Yang
NON-VOLATILE MEMORY WITH INTER-DIE CONNECTION (17825337)
Main Inventor
Shiqian Shao
METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING (17824350)
Main Inventor
Peng Wang
SYSTEMS AND METHODS OF CORRECTING ERRORS IN UNMATCHED MEMORY DEVICES (17827562)
Main Inventor
Venkatesh Prasad RAMACHANDRA
NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT (17828685)
Main Inventor
Jiacen Guo
TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE (17826434)
Main Inventor
Sujjatul Islam
SYSTEMS AND METHODS OF REDUCING DETECTION ERROR AND DUTY ERROR IN MEMORY DEVICES (17828708)
Main Inventor
Jang Woo Lee
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME (17804184)
Main Inventor
Akihiro TOBIOKA