Texas Instruments Incorporated patent applications on April 10th, 2025
Patent Applications by Texas Instruments Incorporated on April 10th, 2025
Texas Instruments Incorporated: 21 patent applications
Texas Instruments Incorporated has applied for patents in the areas of G06F9/30 (3), H04B1/18 (1), H02M3/156 (1), H02M3/158 (1), H03F1/56 (1) G06F12/128 (2), G01R31/31727 (1), G06F30/367 (1), H10D64/111 (1), H04B1/18 (1)
With keywords such as: configured, circuit, coupled, clock, memory, data, circuitry, output, instruction, and address in patent application abstracts.
Patent Applications by Texas Instruments Incorporated
20250116702. CLOCK SYNCHRONIZATION CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): David P MAGEE of Allen TX US for texas instruments incorporated, Bassem IBRAHIM of Allen TX US for texas instruments incorporated, Vishnu RAVINUTHULA of Dallas TX US for texas instruments incorporated
IPC Code(s): G01R31/317
CPC Code(s): G01R31/31727
Abstract: a device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. the command processing circuit has a command input, a reference frequency output, and a reference phase output. the command input is coupled to the communication interface. the clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. the reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. the clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. the controllable clock source has a frequency control input and a clock output. the frequency control input is coupled to the frequency control output.
Inventor(s): Nischal R of CHIKKABALLAPUR IN for texas instruments incorporated, Dattatreya Baragur SURYANARAYANA of BANGALORE IN for texas instruments incorporated, Bikash PRADHAN of BANGALORE IN for texas instruments incorporated, Vikram GAKHAR of BANGALORE IN for texas instruments incorporated, VishnuVardhan REDDY J of BANGALORE IN for texas instruments incorporated, Preetam TADEPARTHY of BANGALORE IN for texas instruments incorporated
IPC Code(s): G01R31/54, H02H7/12, H02M3/335
CPC Code(s): G01R31/54
Abstract: an example multiphase power converter circuit includes a first power stage is configured to provide a first phase output signal at a first switching output based on a first control signal. the first power stage includes first open fault detection circuitry configured to disable detecting and/or reporting of an open fault condition responsive to the first control signal. a second power stage is configured to provide a second phase output signal at a second switching output based on a second control signal. the second power stage includes second open fault detection circuitry configured to enable detecting and/or reporting of the open fault condition responsive to the second control signal having a value to turn off the second power stage. the second open fault detection circuitry is further configured to detect the open fault condition based on a voltage at the second switching output.
Inventor(s): Shailesh Ghotgalkar of Bangalore IN for texas instruments incorporated, Rajeev Suvarna of Bangalore IN for texas instruments incorporated, Prasanth Viswanathan Pillai of Bangalore IN for texas instruments incorporated, Saravanan G of Bangalore IN for texas instruments incorporated
IPC Code(s): G06F1/08, G06F1/12, G06F11/16, H03K5/135, H03K5/26
CPC Code(s): G06F1/08
Abstract: an example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.
Inventor(s): Barak CHERCHES of Ramat Ha'Kovesh IL for texas instruments incorporated, Uri WEINRIB of Mazkeret Batya IL for texas instruments incorporated
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: in some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.
20250117224. NESTED LOOP CONTROL_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kai Chirca of Dallas TX US for texas instruments incorporated, Timothy D. Anderson of University Park TX US for texas instruments incorporated, Todd T. Hahn of Sugar Land TX US for texas instruments incorporated, Alan L. Davis of Sugar Land TX US for texas instruments incorporated
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30065
Abstract: a nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate fifo, initialized to have a third value. the second value is advanced in response to a tick instruction during execution of a loop. in response to the second value reaching a second threshold, the second register is reset to the initial second value. the nested loop controller further includes a comparator coupled to the second register and to the predicate fifo and configured to provide an outer loop indicator value as input to the predicate fifo when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate fifo when the second value is not equal to the second threshold.
Inventor(s): Duc BUI of Grand Prairie TX US for texas instruments incorporated, Timothy D. ANDERSON of University Park TX US for texas instruments incorporated
IPC Code(s): G06F9/30
CPC Code(s): G06F9/485
Abstract: techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.
Inventor(s): Jason Lynn PECK of Houston TX US for texas instruments incorporated, Gary A. COOPER of Oakmont PA US for texas instruments incorporated, Markus KOESLER of Landshut DE for texas instruments incorporated
IPC Code(s): G06F11/362, G06F11/07
CPC Code(s): G06F11/3656
Abstract: a real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without âbreakingâ the system in which the debug application is executing. the debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. a debug monitor function may be implemented as hardware logic on the same integrated circuit as the processor. higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.
Inventor(s): Sriramakrishan GOVINDARAJAN of Bengaluru IN for texas instruments incorporated, Mihir Narendra MODY of Bengaluru IN for texas instruments incorporated, Prithvi Shankar YEYYADI ANANTHA of Bengaluru IN for texas instruments incorporated
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: an adaptive memory mirroring performance accelerator (ammpa) includes a transaction handling block that dynamically maps the most frequently accessed data segments into faster access memory. the technique creates shadow copies of the most frequently accessed data segments in the faster access memory, which is associated with lower latency. access frequencies of the data segments for which shadow copies are provided are updated dynamically based on use. the technique is flexible for different memory hierarchies.
Inventor(s): Daniel Brad WU of Plano TX US for texas instruments incorporated
IPC Code(s): G06F12/1027
CPC Code(s): G06F12/1027
Abstract: a method includes receiving, by a mmu for a processor core, an address translation request from the processor core and providing the address translation request to a tlb of the mmu; generating, by matching logic of the tlb, an address transaction that indicates whether a virtual address specified by the address translation request hits the tlb; providing the address transaction to a general purpose transaction buffer; and receiving, by the mmu, an address invalidation request from the processor core and providing the address invalidation request to the tlb. the method also includes, responsive to a virtual address specified by the address invalidation request hitting the tlb, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.
Inventor(s): Naveen Bhoria of Plano TX US for texas instruments incorporated, Timothy David Anderson of University Park TX US for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX US for texas instruments incorporated
IPC Code(s): G06F9/30
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. an example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
Inventor(s): Naveen Bhoria of Plano TX US for texas instruments incorporated, Timothy David Anderson of University Park TX US for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX US for texas instruments incorporated
IPC Code(s): G06F12/0891, G06F12/0811, G06F12/0871
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. an example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.
Inventor(s): Ankush Ankush of Bengaluru IN for texas instruments incorporated, Venkateswaran Padmanabhan of Bengaluru IN for texas instruments incorporated, Aayush Garg of Bengaluru IN for texas instruments incorporated, Guha Lakshmanan of Bengaluru IN for texas instruments incorporated, Avishek Pal of Bengaluru IN for texas instruments incorporated
IPC Code(s): G06F30/3308
CPC Code(s): G06F30/3308
Abstract: a method comprises creating an electronic circuit design having a plurality of electronic components, simulating operation of the electronic circuit design, and creating a behavior model of the electronic circuit design. the method further comprises eliminating one or more data points created in the behavior model to generate a trimmed behavior model, generating a real number model based on the trimmed behavior model, the real number model comprising a plurality of weights, and generating a simulation model based on the plurality of weights.
Inventor(s): Saksham Sangwan of Bengaluru IN for texas instruments incorporated, Venkateswaran Padmanabhan of Bengaluru IN for texas instruments incorporated, Guha Lakshmanan of Bengaluru IN for texas instruments incorporated
IPC Code(s): G06F30/367, G06F111/10, G06N3/063
CPC Code(s): G06F30/367
Abstract: a method comprises creating an electronic circuit design having a plurality of electronic components, creating an analog simulation model of the electronic circuit design, and executing the analog simulation model to generate one or more simulation logs representing simulated operation of the electronic circuit design. the method also comprises generating a neural network model based on the one or more simulation logs, the neural network model comprising a plurality of weights and generating a mathematical simulation model based on the neural network model.
Inventor(s): Nitesh Mishra of Chakeri IN for texas instruments incorporated, Hrithik Sahni of New Delhi IN for texas instruments incorporated
IPC Code(s): G11C29/56
CPC Code(s): G11C29/56004
Abstract: systems and methods may perform sequential automatic test pattern generation (atpg) on parallel memory units. in one example, a first array of logic gates may output enable signals to cause multiple memory units to be enabled in parallel. test pattern generation and test control logic may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units. the systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
Inventor(s): Isaac Cohen of Dix Hills NY US for texas instruments incorporated
IPC Code(s): H02M1/00, H02M1/08, H02M3/156, H02M3/158
CPC Code(s): H02M1/0003
Abstract: a programmable switch converter controller for a power stage with a switch, an inductor, and a diode, includes a pulse-width modulator. the pulse-width modulator is configured to: generate an on-time interval (ton) that is fixed or proportional to a demand signal proportional to a load adapted to be coupled to an output of the power stage; generate an off-time interval (toff) that is inversely proportional to the product of a voltage across the inductor while the switch is off and a demand signal proportional to the load; initiate ton when toff elapses; and initiate ton responsive to an external trigger signal.
Inventor(s): Tanmay Halder of Bangalore IN for texas instruments incorporated, Anand Subramanian of Bangalore IN for texas instruments incorporated, Laxmi Vivek Tripurari of Bangalore IN for texas instruments incorporated, Anand Kannan of Bangalore IN for texas instruments incorporated
IPC Code(s): H03F1/56, H03F3/45
CPC Code(s): H03F1/56
Abstract: an example apparatus includes: voltage divider circuitry configured to determine a common mode voltage of a differential pair of signals having a first voltage and a second voltage; a first amplifier coupled to the voltage divider circuitry, the first amplifier configured to determine a difference between the common mode voltage and a reference common mode voltage; current compensation circuitry coupled to the first amplifier, the current compensation circuitry configured to generate a first current and a second current responsive to the difference between voltages; and a second amplifier coupled to the voltage divider circuitry and the current compensation circuitry, the second amplifier to compensate the first voltage with the first current and the second voltage with the second current.
Inventor(s): Hakhamanesh MANSOORZARE of Orlando FL US for texas instruments incorporated, Ting-Ta YEN of San Jose CA US for texas instruments incorporated, Jeronimo SEGOVIA-FERNANDEZ of San Jose CA US for texas instruments incorporated, Bichoy BAHR of Allen TX US for texas instruments incorporated
IPC Code(s): H03H9/02, H03H3/007
CPC Code(s): H03H3/0076
Abstract: a method comprises: forming a die including a cavity; coupling an anchor to the die; coupling a first resonator to a side of the anchor, in which the first resonator is suspended over the cavity and is operable to bend towards or away from a bottom of the cavity; and coupling a second resonator to the side of the anchor, in which the second resonator is suspended over the cavity, at least a part of the first resonator is laterally between the side of the anchor and a part of the second resonator, and the first resonator is operable to bend in an opposite direction from the second resonator.
Inventor(s): Huihuang CHEN of SHENZHEN CN for texas instruments incorporated, Yan ZOU of SUZHOU CN for texas instruments incorporated
IPC Code(s): H04L7/00, G06F13/42
CPC Code(s): H03K7/08
Abstract: a circuit includes a microcontroller having a clock output and a data output. the microcontroller includes a serial-peripheral interface (spi) circuit, a pulse-width modulation (pwm) generator, and a central processing unit (cpu). the spi circuit is configured to provide an spi clock signal and an spi data signal to the data output. the pwm generator is configured to provide a continuous pwm signal to the clock output. the cpu is coupled to the spi circuit and the pwm generator, and the cpu has executable instructions configured to synchronize the pwm signal to the spi clock signal.
20250119171. WAKEUP RECEIVER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Danielle Griffith of Richardson TX US for texas instruments incorporated, Tomas Motos of Hamar NO for texas instruments incorporated, Marius Moe of Fetsund NO for texas instruments incorporated
IPC Code(s): H04B1/18, H04B1/16
CPC Code(s): H04B1/18
Abstract: a circuit includes a receiver configured to couple to an antenna, configured to have a wakeup mode and an active mode, and to transition from the wakeup mode to the active mode in response to a wakeup signal received through the antenna. the receiver includes an impedance matching circuit coupled with the antenna, a low-noise amplifier coupled with the impedance matching circuit, a mixer coupled with the low-noise amplifier, a radio-frequency reference clock generator coupled with the mixer, a low-pass filter coupled with the mixer, an analog-to digital-converter coupled with the low-pass filter, and a control circuit configured to transition the receiver from the wakeup mode to the active mode in response to the wakeup signal. the low-noise amplifier, the mixer, the radio frequency reference clock generator, and the analog-to-digital converter are configured to be duty-cycled between a sleep state and an active wakeup receive state during the wakeup mode.
Inventor(s): Jonas HĂśhenberger of Kissing DE for texas instruments incorporated, Ujwal Radhakrishna of San Jose CA US for texas instruments incorporated, Michael Lueders of Freising DE for texas instruments incorporated, Meng-Chia Lee of Allen TX US for texas instruments incorporated, Chang Soo Suh of Allen TX US for texas instruments incorporated, Zhikai Tang of Sunnyvale CA US for texas instruments incorporated, Jungwoo Joh of Allen TX US for texas instruments incorporated, Timothy Bryan Merkin of Princeton TX US for texas instruments incorporated, Stefan Herzer of Marzling DE for texas instruments incorporated, Bernhard Ziegltrum of Freising DE for texas instruments incorporated, Helmut Rinck of Gammelsdorf DE for texas instruments incorporated, Michael Hans Enzelberger-Heim of Munich DE for texas instruments incorporated, Ercuement Hasanoglu of Augsburg DE for texas instruments incorporated
IPC Code(s): H01L29/40, H01L21/027, H01L21/311, H01L29/20, H01L29/66, H01L29/778
CPC Code(s): H10D64/111
Abstract: the present disclosure generally relates to a semiconductor device having a slanted field plate. in an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. the gate is on a surface of the semiconductor substrate. the drain contact and a source contact are on the semiconductor substrate. the field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. the field plate includes multiple field plate portions. each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.
Inventor(s): Robert Martin Higgins of Plano TX US for texas instruments incorporated, Xiaoju Wu of Dallas TX US for texas instruments incorporated, Li Wang of Plano TX US for texas instruments incorporated, Venugopal Balakrishna Menon of Dallas TX US for texas instruments incorporated
IPC Code(s): H01L27/06, H01L21/762
CPC Code(s): H10D84/811
Abstract: a method of manufacturing an electronic device includes forming a shallow trench isolation (sti) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the sti structure and a prospective local oxidation of silicon (locos) portion of a surface of the semiconductor surface layer. the method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the sti structure and to grow an oxide material on the exposed locos portion of the surface of the semiconductor surface layer.
Texas Instruments Incorporated patent applications on April 10th, 2025
- Texas Instruments Incorporated
- G01R31/317
- CPC G01R31/31727
- Texas instruments incorporated
- G01R31/54
- H02H7/12
- H02M3/335
- CPC G01R31/54
- G06F1/08
- G06F1/12
- G06F11/16
- H03K5/135
- H03K5/26
- CPC G06F1/08
- G06F3/06
- CPC G06F3/0619
- G06F9/30
- CPC G06F9/30065
- CPC G06F9/485
- G06F11/362
- G06F11/07
- CPC G06F11/3656
- G06F12/02
- CPC G06F12/0246
- G06F12/1027
- CPC G06F12/1027
- CPC G06F12/128
- G06F12/0891
- G06F12/0811
- G06F12/0871
- G06F30/3308
- CPC G06F30/3308
- G06F30/367
- G06F111/10
- G06N3/063
- CPC G06F30/367
- G11C29/56
- CPC G11C29/56004
- H02M1/00
- H02M1/08
- H02M3/156
- H02M3/158
- CPC H02M1/0003
- H03F1/56
- H03F3/45
- CPC H03F1/56
- H03H9/02
- H03H3/007
- CPC H03H3/0076
- H04L7/00
- G06F13/42
- CPC H03K7/08
- H04B1/18
- H04B1/16
- CPC H04B1/18
- H01L29/40
- H01L21/027
- H01L21/311
- H01L29/20
- H01L29/66
- H01L29/778
- CPC H10D64/111
- H01L27/06
- H01L21/762
- CPC H10D84/811