INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE

Abstract: a memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. the memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. the memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. the memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Inventor(s): Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard

CPC Classification: G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers})

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