US Patent Application 18333498. MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE simplified abstract

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MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Carlos H. Diaz of Los Altos Hills CA (US)


Shy-Jay Lin of Hsinchu County (TW)


Ming-Yuan Song of Hsinchu City (TW)


MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18333498 Titled 'MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE'

Simplified Explanation

This abstract describes a semiconductor device that includes a transistor and an interconnect structure. The transistor has a source region and a drain region. The interconnect structure is placed over the semiconductor substrate and consists of multiple interlayer dielectric layers, a first via, and a memory cell. The interlayer dielectric layers are located above the semiconductor substrate. The first via is embedded in at least two of the interlayer dielectric layers and is electrically connected to the drain region of the transistor. The memory cell is positioned over the same interlayer dielectric layers and is electrically connected to the first via.


Original Abstract Submitted

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

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