US Patent Application 18245969. MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY MODULE simplified abstract
Contents
MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY MODULE
Organization Name
SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor(s)
HARUHIKO Terada of KANAGAWA (JP)
RIICHI Nishino of KANAGAWA (JP)
MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY MODULE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18245969 titled 'MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY MODULE
Simplified Explanation
The patent application describes a method for effectively using a memory module composed of multiple memories.
- Memory access control unit divides write data and its error correction code into multiple memories for writing.
- The presence or absence of verify errors in each memory related to the writing is determined.
- If verify errors occur in any of the memories, the error bit length is acquired from each memory.
- The write control unit determines the success or failure of the writing based on the total bit length of the verify errors.
- If the total bit length falls within the allocated error bit length tolerance, the writing is considered successful.
- If the total bit length falls outside the allocated error bit length tolerance, the writing is considered failed.
Original Abstract Submitted
To effectively use a memory when a plurality of memories is combined to constitute a memory module. A memory access control unit performs writing by dividing write data and an error correction code thereof into a plurality of memories, and acquires presence or absence of occurrence of a verify error in each of the plurality of memories related to the writing. In a case where the verify errors occur in at least any of the plurality of memories, an error bit length acquisition unit acquires bit lengths of the verify errors from the plurality of memories. In the case where the verify errors occur in at least any of the plurality of memories, a write control unit determines that the writing has succeeded if a total bit length of the verify errors falls within a range of a capability allocated to an error bit length tolerance of the error correction code, and determines that the writing has failed if the total bit length of the verify errors falls outside the range of the capability allocated to the error bit length tolerance of the error correction code.
