US Patent Application 18150189. SEMICONDUCTOR CELL STRUCTURE, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD THEREOF simplified abstract

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SEMICONDUCTOR CELL STRUCTURE, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD THEREOF

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chia-Chung Chen of Keelung (TW)

Wen-Shen Chou of Zhubei City (TW)

Yung-Chow Peng of Hsinchu (TW)

Chung-Sheng Yuan of Hsinchu (TW)

Yi-Kan Cheng of Taipei City (TW)

SEMICONDUCTOR CELL STRUCTURE, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18150189 titled 'SEMICONDUCTOR CELL STRUCTURE, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The patent application describes a semiconductor cell structure with two complementary metal oxide silicon (CMOS) components, each connected to a reference voltage through conducting elements. The relationship between the width and channel length of the conducting elements and CMOS components is important.

  • The patent application focuses on a semiconductor cell structure.
  • The structure includes two complementary metal oxide silicon (CMOS) components.
  • A reference voltage is provided to each CMOS component through conducting elements.
  • The width and channel length of the conducting elements and CMOS components are significant.
  • There is a positive relationship between the product of the width and channel length of the first conducting element and CMOS, and the product of the width and channel length of the second conducting element and CMOS.


Original Abstract Submitted

A semiconductor cell structure includes a first complementary metal oxide silicon (CMOS) a second CMOS, a first conducting element, and a second conducting element. The first and second CMOSs are disposed on the substrate and a reference voltage is provided to the first CMOS and the second CMOS respectively through the first conducting element and the second conducting element. A product of a width of the first conducting element multiplied by a channel length of the first CMOS is positively related to a product of a width of the second conducting element multiplied by a channel length of the second CMOS.

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