US Patent Application 18139571. ELECTRODE LAMINATE MANUFACTURING METHOD, ALL-SOLID-STATE BATTERY MANUFACTURING METHOD, ELECTRODE LAMINATE, AND ALL-SOLID-STATE BATTERY simplified abstract

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ELECTRODE LAMINATE MANUFACTURING METHOD, ALL-SOLID-STATE BATTERY MANUFACTURING METHOD, ELECTRODE LAMINATE, AND ALL-SOLID-STATE BATTERY

Organization Name

TOYOTA JIDOSHA KABUSHIKI KAISHA


Inventor(s)

Sachie Akiba of Toyota-shi (JP)

Kazuya Otsu of Miyoshi-shi, Aichi-ken (JP)

Yasutaka Tsutsui of Osaka (JP)

Tsutomu Koshizuka of Osaka (JP)

ELECTRODE LAMINATE MANUFACTURING METHOD, ALL-SOLID-STATE BATTERY MANUFACTURING METHOD, ELECTRODE LAMINATE, AND ALL-SOLID-STATE BATTERY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18139571 titled 'ELECTRODE LAMINATE MANUFACTURING METHOD, ALL-SOLID-STATE BATTERY MANUFACTURING METHOD, ELECTRODE LAMINATE, AND ALL-SOLID-STATE BATTERY

Simplified Explanation

The patent application describes a method for manufacturing an electrode laminate by forming two layers and subjecting them to pressing.

  • The first layer is formed on a surface.
  • The second layer is coated onto the first layer using a slurry.
  • The second layer is then pressed to create the electrode laminate.
  • The first layer is formed in a way that satisfies the condition "0.1<Sa<0.2", where Sa represents the arithmetic mean height of the first layer's surface.


Original Abstract Submitted

A first layer is formed. A second layer is formed by coating a slurry onto a surface of the first layer. The second layer is subjected to pressing, thereby manufacturing an electrode laminate. The forming of the first layer is performed such that a relation of an Expression “0.1<Sa<0.2” is satisfied. In the Expression, Sa (μm) represents an arithmetic mean height of the surface of the first layer.

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