US Patent Application 17974940. METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOF simplified abstract

METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOF

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Sachin Suresh Upadhya of Bengaluru (IN)]]

[[Category:Eldho Pathiyakkara Thombra Mathew of Bengaluru (IN)]]

[[Category:Mayuresh Jyotindra Salelkar of Bengaluru (IN)]]

[[Category:Jinin So of Hwaseong-si (KR)]]

[[Category:Jonggeon Lee of Seoul (KR)]]

[[Category:Kyungsoo Kim of Seoul (KR)]]

METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17974940 titled 'METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOF

Simplified Explanation

The patent application describes a method for operating a NMP-DIMM system, which is a type of memory system.

• The method involves determining a synchronized read latency value for performing a read operation in the NMP-DIMM system.
• This value is determined based on read latency values associated with memory units in the system.
• The method also involves synchronizing data paths in the NMP-DIMM system based on the determined synchronized read latency value.

Original Abstract Submitted

A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.