View source for US Patent Application 17890883. Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer simplified abstract

=Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer=


==Organization Name==

[[Taiwan Semiconductor Manufacturing Company, Ltd.]]


==Inventor(s)==

[[Ching Ju Yang of Hsinchu (TW)]]


[[Yao-Wen Chang of Hsinchu (TW)]]


[[Chih-Chung Lai of Hsinchu County (TW)]]


==Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer - A simplified explanation of the abstract==


*This abstract for appeared for US patent application  number 17890883 Titled 'Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer'

==Simplified Explanation==

This abstract describes an interconnect structure that consists of two interconnect elements. The first interconnect element is connected to a conductive pad layer, which is covered by a capping layer made of titanium nitride. A dielectric layer is placed on top of the capping layer. There is a conductive contact that goes through the dielectric and capping layers, connecting to the first interconnect element through the conductive pad layer. Additionally, there is a conductive via that goes through the dielectric layer, connecting to the second interconnect element.


==Original Abstract Submitted==

An interconnect structure includes at least a first interconnect element and a second interconnect element. A conductive pad layer is disposed over, and electrically coupled to, the first interconnect element. A capping layer is disposed over the conductive pad layer. The capping layer includes titanium nitride. A dielectric layer is disposed over the capping layer. A conductive contact extends vertically through at least a first portion of the dielectric layer and the capping layer. The conductive contact is coupled to the first interconnect element through the conductive pad layer. A conductive via extends vertically through at least a second portion of the dielectric layer. The conductive via is coupled to the second interconnect element.