View source for US Patent Application 17728761. HOMOGENEOUS CHIPLETS CONFIGURABLE AS A TWO-DIMENSIONAL SYSTEM OR A THREE-DIMENSIONAL SYSTEM simplified abstract

=HOMOGENEOUS CHIPLETS CONFIGURABLE AS A TWO-DIMENSIONAL SYSTEM OR A THREE-DIMENSIONAL SYSTEM=


==Organization Name==

[[Microsoft Technology Licensing, LLC]]


==Inventor(s)==

[[Haohua Zhou of Fremont CA (US)]]


[[Xiaoling Xu of Cupertino CA (US)]]


==HOMOGENEOUS CHIPLETS CONFIGURABLE AS A TWO-DIMENSIONAL SYSTEM OR A THREE-DIMENSIONAL SYSTEM - A simplified explanation of the abstract==


*This abstract for appeared for US patent application  number 17728761 Titled 'HOMOGENEOUS CHIPLETS CONFIGURABLE AS A TWO-DIMENSIONAL SYSTEM OR A THREE-DIMENSIONAL SYSTEM'

==Simplified Explanation==

The abstract describes a type of chip called a chiplet that can be configured either as a two-dimensional system or a three-dimensional system. The chiplet system consists of multiple chiplets stacked on top of each other. Each chiplet contains an integrated circuit (IC) die with a logic block and a memory block. The logic block and memory block are connected through paths for transferring data signals. In this example, the first chiplet is stacked with the second chiplet, creating additional paths for transferring data signals between the logic block of the first chiplet and the memory block of the second chiplet, and vice versa. This configuration allows for more efficient data transfer and improved performance.


==Original Abstract Submitted==

Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.