US Patent Application 17715964. MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY simplified abstract
Contents
MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Kerem Akarvardar of Hsinchu (TW)
Win-San Khwa of Taipei City (TW)
Meng-Fan Chang of Taichung City (TW)
Hon-Sum Philip Wong of Stanford CA (US)
MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 17715964 Titled 'MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY'
Simplified Explanation
The abstract describes a memory array and its components, including memory cells, floating gate transistors, bit lines, and word lines. The memory cells consist of a capacitor and an electrically programmable non-volatile memory (NVM) connected in series, along with a write transistor. The floating gate transistors are connected to the capacitors in a column of memory cells, while the bit lines are connected to the electrically programmable NVMs in a row of memory cells. The word lines are connected to the gate terminals of the write transistors in a row of memory cells.
Original Abstract Submitted
A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.
