Texas instruments incorporated (20240113717). OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR simplified abstract
Contents
- 1 OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR
Organization Name
texas instruments incorporated
Inventor(s)
YOGESH Ramadass of SAN JOSE CA (US)
OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113717 titled 'OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR
Simplified Explanation
The clock circuit described in the abstract includes a voltage-controlled oscillator (VCO), a frequency-locked loop (FLL), a microelectromechanical system (MEMS) resonator-based oscillator, and a multiplexer. The VCO has a control input and a first clock output, while the FLL has an FLL input and a control output that is coupled to the VCO's control input. The MEMS resonator-based oscillator has a second clock output, which is connected to the multiplexer. The multiplexer has a selection input that determines which clock output is sent to the FLL input.
- The clock circuit utilizes a VCO to generate a clock signal with a frequency that can be controlled by an input voltage.
- The FLL ensures that the output frequency of the VCO is locked to a reference frequency, providing stability and accuracy to the clock signal.
- The MEMS resonator-based oscillator offers a secondary clock output, which can be selected by the multiplexer to be fed into the FLL for further processing and synchronization.
Potential Applications
The technology described in this patent application could be applied in various fields such as telecommunications, data communication, and precision timing applications.
Problems Solved
This technology solves the problem of generating accurate and stable clock signals for electronic devices that require precise timing and synchronization.
Benefits
The benefits of this technology include improved accuracy, stability, and control over clock signals, leading to enhanced performance and reliability of electronic systems.
Potential Commercial Applications
Potential commercial applications of this technology include telecommunications equipment, network infrastructure, data centers, and high-precision measurement devices.
Possible Prior Art
One possible prior art for this technology could be the use of traditional crystal oscillators or phase-locked loops in clock circuits for frequency control and synchronization.
Unanswered Questions
How does this technology compare to other clock circuit designs in terms of power consumption and size?
This article does not provide information on the power consumption and size of the clock circuit compared to other designs.
What are the specific requirements for integrating this technology into existing electronic systems?
The article does not address the specific integration requirements of this technology into existing electronic systems.
Original Abstract Submitted
a clock circuit includes a voltage-controlled oscillator (vco) having a control input and a first clock output. the clock circuit includes a frequency-locked loop (fll) having an fll input and a control output, the control output coupled to the control input. a microelectromechanical system (mems) resonator-based oscillator has a second clock output. a multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. the first multiplexer input is coupled to the first clock output. the second multiplexer input is coupled to the second clock output. the multiplexer output is coupled to the fll input.
