Taiwan semiconductor manufacturing company, ltd. (20240113206). MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE simplified abstract
Contents
- 1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Yu-Lien Huang of Hsinchu County (TW)
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240113206 titled 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Simplified Explanation
The method described in the patent application involves forming a multilayer interconnection structure over a carrier substrate, depositing an interlayer dielectric layer, forming a source/drain contact, depositing a semiconductive layer, patterning the semiconductive layer to form a semiconductor fin, and forming a gate structure across the semiconductor fin. The semiconductor fin is then patterned to create recesses, in which source/drain epitaxial structures are formed to connect to the source/drain contact.
- Formation of multilayer interconnection structure over carrier substrate
- Deposition of interlayer dielectric layer
- Formation of source/drain contact
- Deposition and patterning of semiconductive layer to form semiconductor fin
- Formation of gate structure across semiconductor fin
- Patterning of semiconductor fin to create recesses
- Formation of source/drain epitaxial structures in recesses to connect to source/drain contact
Potential Applications
This technology could be applied in the manufacturing of advanced semiconductor devices, such as high-performance transistors for integrated circuits.
Problems Solved
This technology helps in improving the performance and efficiency of semiconductor devices by enhancing the connection between the source/drain contact and the epitaxial structures.
Benefits
The benefits of this technology include increased conductivity, reduced resistance, and improved overall functionality of semiconductor devices.
Potential Commercial Applications
One potential commercial application of this technology could be in the production of high-speed processors for computers and other electronic devices.
Possible Prior Art
One possible prior art for this technology could be the use of similar methods in the fabrication of semiconductor devices in the semiconductor industry.
Unanswered Questions
How does this technology impact the overall cost of manufacturing semiconductor devices?
The article does not provide information on the cost implications of implementing this technology in semiconductor device manufacturing processes.
What are the potential limitations or challenges associated with the implementation of this technology on a larger scale?
The article does not address any potential limitations or challenges that may arise when scaling up the use of this technology in semiconductor device production.
Original Abstract Submitted
a method includes forming a first multilayer interconnection structure over a carrier substrate. a first interlayer dielectric (ild) layer is deposited over the first multilayer interconnection structure. a first source/drain contact is formed in the first ild layer. after forming the first source/drain contact, a semiconductive layer is formed over the first source/drain contact and the first ild layer. the semiconductive layer is patterned to form a semiconductor fin over the first source/drain contact. a gate structure is formed across the semiconductor fin. the semiconductor fin is patterned to form a first recess and a second recess in the semiconductor fin, such that the first recess exposes the first source/drain contact. first and second source/drain epitaxial structures are respectively formed in the first and second recesses of the semiconductor fin such that the first source/drain epitaxial structure is electrically connected to the first source/drain contact.
