SPACER FORMATION METHOD FOR MULTI-GATE DEVICE AND STRUCTURES THEREOF

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

SPACER FORMATION METHOD FOR MULTI-GATE DEVICE AND STRUCTURES THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240113203 titled 'SPACER FORMATION METHOD FOR MULTI-GATE DEVICE AND STRUCTURES THEREOF

Simplified Explanation

The method described in the abstract involves depositing spacer layers with different etch rates over a semiconductor fin structure to create a trench with a funnel shape, followed by the formation of inner spacers along the trench sidewalls. The semiconductor channel layers are removed from the source/drain region to facilitate this process.

The method involves providing a fin structure with multiple semiconductor channel layers and a gate on a substrate.
A first spacer layer with a certain etch rate is deposited over the gate and fin in the source/drain region.
A second spacer layer with a lower etch rate than the first layer is then deposited over the first spacer layer.
The semiconductor channel layers are removed from the source/drain region to form a trench with a funnel shape.
Inner spacers are formed along the sidewalls of the trench.

Potential Applications

This technology could be applied in the manufacturing of advanced semiconductor devices, such as high-performance transistors and integrated circuits.

Problems Solved

This method helps in improving the performance and efficiency of semiconductor devices by optimizing the structure of the source/drain region.

Benefits

The method allows for better control over the formation of the trench structure, leading to enhanced device performance and reliability.

Potential Commercial Applications

Potential commercial applications of this technology include the production of faster and more energy-efficient electronic devices for various industries.

Possible Prior Art

One possible prior art could be the use of different spacer materials with varying etch rates in semiconductor device fabrication processes to control the formation of trench structures.

Unanswered Questions

How does the etch rate of the spacer layers affect the final trench shape and dimensions?

The abstract mentions that the second spacer layer has a lower etch rate than the first layer, but it does not elaborate on how this difference impacts the trench formation process.

Are there any specific challenges or limitations associated with the formation of inner spacers along the trench sidewalls?

While the abstract mentions the formation of inner spacers, it does not discuss any potential difficulties or constraints that may arise during this step of the process.

Original Abstract Submitted

a method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. a first spacer layer is deposited over the gate and over the fin in a source/drain region. the first spacer layer has a first etch rate. a second spacer layer is deposited over the first spacer layer. the second spacer layer has a second etch rate less than the first etch rate. the plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. after forming the trench, inner spacers are formed along a sidewall surface of the trench. in various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.

Taiwan semiconductor manufacturing company, ltd. (20240113203). SPACER FORMATION METHOD FOR MULTI-GATE DEVICE AND STRUCTURES THEREOF simplified abstract

Contents

SPACER FORMATION METHOD FOR MULTI-GATE DEVICE AND STRUCTURES THEREOF

Organization Name

Inventor(s)